LMX2541SQE2060E/NOPB National Semiconductor, LMX2541SQE2060E/NOPB Datasheet - Page 47

• Manufacturer Part Number: LMX2541SQE2060E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2541SQE2060E/NOPB

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 2.24GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 2.24GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2541SQE2060ETR

There are restrictions when using digital lock detect, based on the phase detector frequency (f
VCO frequency (f
size (ε
size that is selected.
The first restriction involves the minimum window size (ε
programmable value of 13.5 ns for valid operation of the digital lock detect. Possible remedies for this solution would be reducing
the delta sigma order, using a higher VCO frequency and using a larger VCO_DIV value, or using analog lock detect.
The second restriction is the maximum window size (ε
programmable window size of 3.5 ns, then this indicates that the digital lock detect can not be used in this condition. Possible
remedies for this could be to decrease the phase detector frequency, use analog lock detect, decrease the delta sigma order, or
decrease the VCO frequency.
The third restriction comes from rearranging the equation for ε
In addition to this restriction on the maximum phase detector rate, recall that there are also restrictions on the maximum phase
detector rate implied by the electrical specifications ( f
f
VCO
(MHz)
1200
1200
1200
1530
1530
1530
1800
1800
1800
2000
2000
2000
3000
3000
3000
4000
4000
4000
f
400
400
400
500
500
500
600
600
600
VCO
All
/ N
max
Min
ORDER
), and the third involves further restrictions on the maximum phase detector frequency that are implied by the window
).
0
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
4
3
2
VCO
(ns)
20.0
10.0
16.0
13.3
ε
0.0
5.0
8.0
4.0
6.7
3.3
6.7
3.3
1.7
5.2
2.6
1.3
4.4
2.2
1.1
4.0
2.0
1.0
2.7
1.3
0.7
2.0
1.0
0.5
min
). The first restriction involves a minimum window size (ε
(104, f
ε = 3.5 ns
102.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
46.2
80.0
92.3
Min
VCO
/ 12)
(104, f
ε = 5.5 ns
102.0
104.0
104.0
104.0
100.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
30.8
38.5
46.2
80.0
92.3
80.3
91.8
Min
Maximum Possible Phase Detector Frequency (MHz)
3.5 ns
VCO
13.5 ns
f
PD
/ 12)
≤
≤
1 / ( ε
PD
max
≥
ε
min
max
≤
ε
). If the calculated maximum window size is less than the minimum
(104, f
). This minimum window size can not be greater than the maximum
min
104 MHz ) and by the minimum continuous N divider value (f
min
ε = 7.5 ns
= 1/f
max
= 2
47
102.0
104.0
104.0
104.0
100.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
104.0
FAIL
FAIL
FAIL
FAIL
FAIL
+ ε
30.8
38.5
40.0
46.2
63.2
80.0
92.3
80.3
91.8
Min
.
VCO
PD
ORDER-1
max
- ε
/ 12)
+ 2 ns )
min
/ f
- 2 ns
(87.0, f
VCO
min
ε = 9.5 ns
), the second one involves a maximum window
FAIL
FAIL
FAIL
FAIL
30.8
33.3
38.5
40.0
46.2
63.2
80.0
87.0
80.3
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
87.0
Min
VCO
/ 12)
PD
(74.1, f
), Modulator Order (ORDER), and
ε = 11.5 ns
FAIL
FAIL
FAIL
26.7
30.8
33.3
38.5
40.0
46.2
63.2
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
74.1
Min
VCO
/ 12)
(64.5, f
ε = 13.5 ns
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FAIL
FAIL
26.7
30.8
33.3
38.5
31.6
40.0
46.2
63.2
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
64.5
Min
VCO
/ 12)
PD
≤