LMK03000CISQ/NOPB National Semiconductor, LMK03000CISQ/NOPB Datasheet - Page 8

• Manufacturer Part Number: LMK03000CISQ/NOPB
• Description: IC CLOCK CONDITIONER PREC 48-LLP
• Manufacturer: National Semiconductor
• Type: Clock Conditionerr

Specifications of LMK03000CISQ/NOPB

• Pll: Yes
• Input: Clock
• Output: LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.296GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Frequency-max: 1.296GHz
• For Use With: LMK03000CEVAL - BOARD EVALUATION LMK03000C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMK03000CISQ; LMK03000CISQTR

www.national.com
Jitter
t
V
ΔV
V
ΔV
I
I
I
Jitter
t
V
V
V
V
V
I
I
V
V
V
V
I
I
SKEW
SA
SB
SAB
SKEW
IH
IL
IH
IL
OD
OS
OH
OL
OD
IH
IL
OH
OL
IH
IL
Symbol
OD
OS
ADD
ADD
Additive RMS Jitter
CLKoutX to CLKoutY
Differential Output Voltage
Change in magnitude of V
complementary output states
Output Offset Voltage
Change in magnitude of V
complementary output states
Clock Output Short Circuit Current
single-ended
Clock Output Short Circuit Current
differential
Additive RMS Jitter
CLKoutX to CLKoutY
Output High Voltage
Output Low Voltage
Differential Output Voltage
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
High-Level Output Voltage
Low-Level Output Voltage
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
Clock Distribution Section
Parameter
Clock Distribution Section
(Note
(Note
(Note
(Note
12)
12)
OD
OS
14)
14)
for
for
Digital MICROWIRE Interfaces
Digital LVTTL Interfaces
(Note
R
Distribution Path =
765 MHz
Bandwidth =
12 kHz to 20 MHz
Equal loading and identical clock
configuration
R
R
R
R
R
Single-ended outputs shorted to GND
Complementary outputs tied together
R
Distribution Path =
765 MHz
Bandwidth =
12 kHz to 20 MHz
Equal loading and identical clock
configuration
Termination = 50 Ω to Vcc - 2 V
Termination = 50 Ω to Vcc - 2 V
R
V
V
I
I
V
V
OH
OL
(Note
IH
IL
IH
IL
L
L
L
L
L
L
L
L
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
= -500 µA
= 0
= 0
= Vcc
= +500 µA
= Vcc
12,
12,
8
Note
Note
Conditions
13) - LVPECL Clock Outputs
13) - LVDS Clock Outputs
(Note
(Note
CLKoutX_MUX
= Bypass (no
divide or delay)
CLKoutX_MUX
= Divided (no
delay)
CLKoutX_DIV =
4
CLKoutX_MUX
= Bypass (no
divide or delay)
CLKoutX_MUX
= Divided (no
delay)
CLKoutX_DIV =
4
15)
16)
1.070
-40.0
Vcc -
Min
-5.0
-5.0
-5.0
250
660
-30
-50
-35
-24
-12
-30
2.0
0.4
1.6
Vcc -
Vcc -
1.25
0.98
Typ
350
810
1.8
±4
±3
20
75
20
75
1.370
Max
450
965
Vcc
Vcc
0.8
5.0
5.0
0.4
0.4
5.0
5.0
30
50
35
24
12
30
Units
mV
mV
mV
mA
mA
mV
µA
µA
µA
µA
ps
ps
fs
fs
V
V
V
V
V
V
V
V
V