AD9516-3BCPZ Analog Devices Inc, AD9516-3BCPZ Datasheet - Page 74

• Manufacturer Part Number: AD9516-3BCPZ
• Description: IC CLOCK PLL/VCO 2GHZ 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-3BCPZ

• Pll: Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 2GHz
• No. Of Outputs: 10
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9516-3/PCBZ - BOARD EVAL FOR AD9516-3 2.0GHZ
• Lead Free Status / Rohs Status: Compliant

AD9516-3
Reg.
Addr.
(Hex)
0x194
0x195
0x196
0x197
0x198
Table 59. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex)
0x199
0x19A
0x19B
Bits
4
[3:0]
1
0
[7:4]
[3:0]
7
6
5
4
[3:0]
1
0
Bits
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
Name
Divider 1 start high
Divider 1 phase offset
Divider 1 direct to output
Divider 1 DCCOFF
Divider 2 low cycles
Divider 2 high cycles
Divider 2 bypass
Divider 2 nosync
Divider 2 force high
Divider 2 start high
Divider 2 phase offset
Divider 2 direct to output
Divider 2 DCCOFF
Name
Low Cycles Divider 3.1
High Cycles Divider 3.1
Phase Offset Divider 3.2
Phase Offset Divider 3.1
Low Cycles Divider 3.2
High Cycles Divider 3.2
Description
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high. A value of
0x0 means that the divider is high for one input clock cycle (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1)of 3.2 divider input during which 3.2 output stays high. A value
of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Description
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
0: OUT4 and OUT5 are connected to Divider 2 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Rev. A | Page 74 of 80