AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet
AD9516-5BCPZ-REEL7
Specifications of AD9516-5BCPZ-REEL7
Related parts for AD9516-5BCPZ-REEL7
AD9516-5BCPZ-REEL7 Summary of contents
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... PLL that can be used with an external VCO/VCXO. 1 The AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-5 is used, it refers to that specific member of the AD9516 family. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...
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... AD9516-5 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 6 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Timing Diagrams ..................................................................... 8 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................... 9 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ...
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... Thermal Performance ..................................................................... 49 Register Map Overview .................................................................. 50 Register Map Descriptions ............................................................. 54 REVISION HISTORY 1/09—Revision 0: Initial Version Application Notes ............................................................................ 72 Using the AD9516 Outputs for ADC Clock Applications .... 72 LVPECL Clock Distribution ...................................................... 72 LVDS Clock Distribution ........................................................... 73 CMOS Clock Distribution ......................................................... 73 Outline Dimensions ........................................................................ 74 ...
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... AD9516-5 SPECIFICATIONS Typical (typ) is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5. otherwise noted. Minimum (min) and maximum (max) values are given over full V POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ VS 3.135 3.3 VS_LVPECL 2.375 VCP VS RSET Pin Resistor 4.12 CPRSET Pin Resistor 5 ...
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... Selected by 0x017[1:0] and 0x018[4] 3.5 ns 0x017[1:0] = 00b, 01b, 11b; 0x018[ 7.5 ns 0x017[1:0] = 00b, 01b, 11b; 0x018[ 3.5 ns 0x017[1:0] = 10b; 0x018[ 0x017[1:0] = 00b, 01b, 11b; 0x018[ 0x017[1:0] = 00b, 01b, 11b; 0x018[ 0x017[1:0] = 10b; 0x018[ Rev Page AD9516 PFD ...
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... AD9516-5 CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Input Sensitivity, Differential Input Level, Differential Input Common-Mode Voltage Input Common-Mode Range, V CMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance 1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V CLOCK OUTPUTS Table 4 ...
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... Rev Page AD9516-5 Unit Test Conditions/Comments Single-ended; termination = 10 pF MHz See Figure load load Test Conditions/Comments Termination = 50 Ω to VS_LVPECL − amplitude = 810 mV 20% to 80%, measured differentially 80% to 20%, measured differentially See Figure 33 See Figure 32 Termination = 100 Ω ...
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... AD9516-5 Parameter Delay Variation with Temperature 5 Short Delay Range Zero Scale Full Scale Long Delay Range 5 Zero Scale Full Scale 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Corresponding CMOS drivers set to OUTxA for noninverting, and OUTxB for inverting ...
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... Distribution section only; does not include PLL Input slew rate > 1 V/ns −110 dBc/Hz −120 dBc/Hz −127 dBc/Hz −136 dBc/Hz −144 dBc/Hz −147 dBc/Hz −154 dBc/Hz Rev Page AD9516-5 ...
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... AD9516-5 Parameter CLK = 1 GHz, Output = 50 MHz Divider = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 7. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER LVPECL = 245.76 MHz; PLL LBW = 125 Hz LVPECL = 122.88 MHz ...
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... Min Typ Max Unit Test Conditions/Comments CS has an internal 30 kΩ pull-up resistor 2 μA 110 μ SCLK has an internal 30 kΩ pull-down resistor 2.0 V 0.8 V 110 μA 1 μ Rev Page AD9516-5 Test Conditions/Comments Incremental additive jitter ...
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... AD9516-5 Parameter SDIO (WHEN INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/t ) CLK Pulse Width High, t HIGH Pulse Width Low, t ...
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... PLL operating; typical closed-loop configuration (this number is included in all other power measurements) 220 mW AD9516 core only, all drivers off, PLL off, VCO divider off, and delay blocks off; the power consumption of the configuration of the user can be derived from this number and the power deltas that follow ...
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... AD9516-5 Parameter CMOS Channel (Divider Plus Output Driver) CMOS Driver (Second in Pair) CMOS Driver (First in Second Pair) Fine Delay Block Min Typ Max Unit Test Conditions/Comments 100 mW Static; no CMOS output on to one CMOS output on (that is, enabling OUT8A starting with OUT8 and OUT9 off ) ...
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... 0.3 V board in still air in accordance with EIA/JESD51-7. −1 +1.2 V −0 0.3 V Table 16. −0 0.3 V Package Type 64-Lead LFCSP (CP-64-4) ESD CAUTION −0 0.3 V −0 0.3 V 150°C −65°C to +150°C 300°C Rev Page AD9516-5 θ Unit JA 22 °C/W ...
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... I Differential CLK clock input 14 I Differential CLK clock input LVPECL LVPECL VS 1 PIN 1 INDICATOR VCP AD9516-5 8 TOP VIEW NC 9 (Not to Scale CLK 13 CLK LVPECL LVPECL Figure 6. Pin Configuration Description 3.3 V Power Pins. Reference Monitor (Output). This pin has multiple selectable outputs; ...
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... PLL is not used. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. This pin can be left unconnected when the PLL is not used. The exposed pad must be connected to GND. Rev Page AD9516-5 ...
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... AD9516-5 TYPICAL PERFORMANCE CHARACTERISTICS 300 3 CHANNELS—6 LVPECL 280 260 240 220 200 3 CHANNELS—3 LVPECL 180 160 2 CHANNELS—2 LVPECL 140 120 1 CHANNEL—1 LVPECL 100 0 500 1000 1500 FREQUENCY (MHz) Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs 180 2 CHANNELS—4 LVDS ...
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... Figure 15. LVPECL Output (Differential) @ 1600 MHz 0.4 0.2 0 –0.2 –0.4 2 Figure 16. LVDS Output (Differential) @ 100 MHz 0.4 0.2 0 –0.2 –0 Figure 17. LVDS Output (Differential) @ 800 MHz 2.8 1.8 0.8 –0 Rev Page AD9516 TIME (ns TIME (ns 100 TIME (ns) Figure 18. CMOS Output @ 25 MHz 5 ...
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... AD9516-5 2.8 1.8 0.8 –0 TIME (ns) Figure 19. CMOS Output @ 250 MHz 1600 1400 1200 1000 800 0 1 FREQUENCY (GHz) Figure 20. LVPECL Differential Swing vs. Frequency 700 600 500 0 100 200 300 400 500 FREQUENCY (MHz) Figure 21. LVDS Differential Swing vs. Frequency Figure 22. CMOS Output Swing vs. Frequency and Capacitive Load – ...
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... Figure 29. Phase Noise (Additive) CMOS @ 250 MHz, Divide-by-4 –120 –130 –140 –150 –160 10M 100M 1k Figure 30. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz Rev Page AD9516-5 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 1k 10k 100k ...
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... AD9516-5 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave has a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, have a variation from the ideal phase progression over time. This variation is called phase jitter. Although many causes ...
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... CPRSET VCP LOCK DETECT HOLD PHASE CHARGE FREQUENCY PUMP DETECTOR LVPECL LVPECL LVPECL ΔT LVDS/CMOS ΔT ΔT LVDS/CMOS ΔT AD9516 STATUS OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 OUT5 OUT5 OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B) ...
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... AD9516-5 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9516 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 47 and Table 48 through Table 57). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. ...
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... COUNTERS N DIVIDER DIVIDE BY 0 DIVIDE DIVIDE DIVIDE DIVIDE BY DIVIDE DIVIDE BY DIVIDE Figure 32. Clock Distribution or External VCO < 1600 MHz (Mode 1) Rev Page AD9516-5 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL OUT1 OUT1 OUT2 OUT2 LVPECL ...
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... AD9516-5 Mode 2: High Frequency Clock Distribution—CLK or External VCO >1600 MHz The AD9516 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-2/divide-by-3/divide-by-4/divide-by-5/ divide-by-6) ...
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... VCO STATUS A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER DIVIDE BY 0 DIVIDE DIVIDE DIVIDE DIVIDE BY DIVIDE DIVIDE BY DIVIDE Rev Page AD9516-5 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL OUT1 OUT1 OUT2 OUT2 LVPECL OUT3 OUT3 OUT4 ...
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... ADIsimCLK™ free program that can help with the design and exploration of the capabilities and features of the AD9516, including the design of the PLL loop filter. ADIsimCLK Version 1.2 (or later) can be used for modeling the AD9516 loop filter available at www.analog.com/clocks. Phase Frequency Detector (PFD) ...
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... C1 Figure 35. Example of External Loop Filter for PLL PLL Reference Inputs The AD9516 features a flexible PLL reference input circuit that allows a fully differential input or two separate single-ended inputs. The input frequency range for the reference inputs is specified in Table 2. Both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals ...
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... VCO REF When the divide is a fixed divide 16, or 32. By using combinations of DM and FD modes, the AD9516 can achieve values of N all the way down Table 24 shows how a 10 MHz reference input may be locked to any integer multiple of N. Note that the same value of N can be derived in different ways, as illustrated by the case ...
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... DM Analog Lock Detect (ALD) The AD9516 provides an ALD function that can be selected for use at the LD pin. There are two versions of ALD. • N-channel open-drain lock detect. This signal requires a pull- up resistor to the positive supply, VS. The output is normally high with short, low going pulses. Lock is indicated by the minimum duty cycle of the low going pulses. • ...
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... Figure 38. Current Source Lock Detect External VCXO/VCO Clock Input (CLK/ CLK ) CLK is a differential input that can be used to drive the AD9516 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors ...
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... Use of the current source lock detect mode is recommended to avoid this situation (see the Current Source Digital Lock Detect section). When in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. Rev Page AD9516-5 ...
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... Frequency Status Monitors The AD9516 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. Figure diagram that shows their location in the PLL ...
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... The clock outputs have either LVPECL or LVDS/CMOS signal levels at the pins. The AD9516 has five clock channels: three channels are LVPECL (six outputs); two channels are LVDS/CMOS (up to four LVDS outputs eight CMOS outputs). ...
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... AD9516-5 Table 26. Settings for Routing VCO Divider Input Directly to LVPECL Outputs Register Setting Selection 0x1E1[ VCO divider selected 0x192[ Direct to output OUT0, OUT1 0x195[ Direct to output OUT2, OUT3 0x198[ Direct to output OUT4, OUT5 Clock Frequency Division The total frequency division is a combination of the VCO divider (when used) and the channel divider ...
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... Table 33. Setting Phase Offset and Division for Divider 0, Divider 1, and Divider 2 Divider Note that the value stored in the register equals the number of cycles minus one. For example, 0x190[7:4] = 0001b equals two low cycles ( for Divider 0. Rev Page AD9516-5 D Output Duty Cycle DCCOFF = 1 DCCOFF = 0 Channel 1 (divider Same as input ...
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... AD9516-5 Let Δ = delay (in seconds). t Δ = delay (in cycles of clock signal at input period of the clock signal at the input of the divider seconds). Φ × SH[ × PO[ × PO[ × PO[ × PO[0] The channel divide-by is set high cycles and M = low cycles. Case 1 For Φ ≤ 15: Δ ...
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... M ) 50% X.2 X 50% X.2 X 50% X.2 X 50% X.2 X 50% X.2 X 50% X.2 X.2 Rev Page AD9516 X.1 X.2 Output Duty Cycle X.1 X.1 X.2 X.2 Bypassed Bypassed 50% Bypassed Bypassed (1 + X%)/3 Bypassed Bypassed (2 + X%)/5 Even Bypassed 50 X.1 X.1 Bypassed 50% ...
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... X.1 X.1 50% Case 4 When Φ X.1 50% Δ (Φ − 50% X.1 Fine Delay Adjust (Divider 3 and Divider 4) 50% Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes an analog delay element that can be programmed to give variable 50% time delays (Δ ( X.1 X.2 X.1 VCO X%)/ CLK DIVIDER X ...
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... SYNC signal with respect to the clock edges inside the AD9516. The delay from the rising edge to the beginning of synchronized output clocking is between 14 and 15 cycles of clock at the channel divider input, ...
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... SYNC operation. Between outputs and after synchronization, this allows for the setting of phase offsets. The AD9516 outputs are in pairs, sharing a channel divider per pair (two pairs of pairs, four outputs, in the case of CMOS). The synchronization conditions apply to both outputs of a pair. ...
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... However, when the CMOS A output is powered up, the CMOS B output can be powered on or off separately. RESET MODES The AD9516 has several ways to force the chip into a reset OUT condition that restores all registers to their default values and makes these settings active. ...
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... AD9516-5 When the AD9516 power-down, the chip is in the following state: • The PLL is off (asynchronous power-down). • The CLK input buffer is off. • All dividers are off. • All LVDS/CMOS outputs are off. • All LVPECL outputs are in safe off mode. ...
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... PORT SDIO 22 Figure 49. Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT A write or a read operation to the AD9516 is initiated by pulling CS low. CS stall high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (see these modes, CS can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte ...
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... In MSB first mode, subsequent bytes increment the address. MSB/LSB FIRST TRANSFERS The AD9516 instruction word and byte data can be MSB first or LSB first. Any data written to 0x000 must be mirrored; the upper four bits ([7:4]) must mirror the lower four bits ([3:0]). ...
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... Figure 54. Timing Diagram for Serial Control Port Register Read A9 A10 A11 A12 REGISTER (N) DATA Rev Page LSB REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA t C DON'T CARE DON'T CARE REGISTER ( DATA AD9516-5 DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE D7 DON'T CARE ...
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... AD9516 SCLK SDIO Table 45. Serial Control Port Timing Parameter Description t Setup time between data and the rising edge of SCLK DS t Hold time between data and the rising edge of SCLK DH t Period of the clock CLK t Setup time between the CS falling edge and the SCLK rising edge (start of communication cycle) ...
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... Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 JC Ψ Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) JT The AD9516 is specified for a case temperature (T that T is not exceeded, an airflow source can be used. CASE Use the following equation to determine the junction ...
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... AD9516-5 REGISTER MAP OVERVIEW Register addresses that are not listed in Table 47 (as well as ones marked unused) are not used and writing to those registers has no effect. The user should only write the default value to the register addresses marked reserved. Table 47. Register Map Overview ...
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... OUT7 select CMOS B LVDS/CMOS OUT8 OUT8 select CMOS B LVDS/CMOS OUT9 OUT9 select CMOS B LVDS/CMOS Unused Rev Page AD9516-5 Bit 2 Bit 1 Bit 0 (LSB) OUT6 delay bypass OUT6 ramp current OUT7 delay bypass OUT7 ramp current OUT8 delay bypass OUT8 ramp current OUT9 delay ...
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... AD9516-5 Addr Bit 7 (Hex) Parameter (MSB) Bit 6 LVPECL Channel Dividers 190 Divider 0 (PECL) 191 Divider 0 Divider 0 bypass nosync 192 193 Divider 1 (PECL) 194 Divider 1 Divider 1 bypass nosync 195 196 Divider 2 (PECL) 197 Divider 2 Divider 2 bypass nosync 198 LVDS/CMOS Channel Dividers 199 Divider 3 Low Cycles Divider 3 ...
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... System 230 Power-down and SYNC 231 Update All Registers 232 Update all registers Bit 5 Bit 4 Bit 3 Reserved Unused Unused Rev Page AD9516-5 Bit 2 Bit 1 Bit 0 (LSB) Power- Power- Soft SYNC down down SYNC distribution reference Update all registers (self-clearing bit) Default ...
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... AD9516-5 REGISTER MAP DESCRIPTIONS Table 48 through Table 57 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is indicated by the brackets. For example, [3] refers to Bit 3, and [5:2] refers to the range of bits from Bit 5 through Bit 2. ...
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... CP 0 0.6 1 1.2 0 1.8 1 2.4 0 3.0 1 3.6 0 4.2 1 4.8 (default) Charge Pump Mode High impedance state. Force source current (pump up). Force sink current (pump down). Normal operation (default). Mode Normal operation. Asynchronous power-down (default). Normal operation. Synchronous power-down. Rev Page AD9516-5 ...
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... AD9516-5 Reg. Addr (Hex) Bit(s) Name Description 016 [5] Reset A and B Reset A and B counters (part of N divider). counters [ normal (default). This register is not self-clearing. [ reset A and B counters. 016 [4] Reset all Reset R, A, and B counters. This register is not self-clearing. counters [ normal (default). [ reset R, A, and B counters. ...
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... Digital lock detect (DLD) (active low LVL Holdover active (active low LVL LD pin comparator output (active low). Antibacklash Pulse Width (ns) 2.9 (default) 1.3 6.0 2.9 PFD Cycles to Determine Lock 5 (default 255 Action Do nothing on SYNC (default). Asynchronous reset. Synchronous reset. Do nothing on SYNC. Rev Page AD9516-5 ...
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... AD9516-5 Reg. Addr (Hex) Bit(s) Name Description 01A [6] Reference Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect frequency the CLK frequency monitor’s detection threshold (see Table 13, REF1, REF2, and CLK frequency status monitor). monitor [ ...
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... Unselected reference to PLL (not available when in differential mode LVL Status of selected reference (status of differential reference); active low LVL Status of unselected reference (not available in differential mode); active low LVL Status of REF1 frequency (active low LVL Status of REF2 frequency (active low). Rev Page AD9516-5 ...
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... AD9516-5 Reg. Addr (Hex) Bit(s) Name Description [4] [ 01C [7] Disable Disable or enable the switchover deglitch circuit. switchover [ enable switchover deglitch circuit (default). deglitch [ disable switchover deglitch circuit. 01C [6] Select REF2 If Register 0x01C[ select reference for PLL. [ select REF1 (default). [ select REF2. 01C ...
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... OUT6 ramp Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors capacitors and the ramp current sets the full-scale delay. [5] [4] [3] Number of Capacitors (default Rev Page AD9516-5 ...
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... AD9516-5 Reg. Addr (Hex) Bit(s) Name Description 0A1 [2:0] OUT6 ramp Ramp current for the delay function. The combination of the number of capacitors and the ramp current current sets the full-scale delay. [2] [1] [0] Current (μ 0A2 [5:0] OUT6 delay Selects the fraction of the full-scale delay desired (6-bit binary). 000000 gives zero delay. ...
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... Selects the fraction of the full-scale delay desired (6-bit binary). 000000 gives zero delay. fraction Only delay values decimals (101111b; 0x02F) are supported (default: 0x00 (default 200 (default) 1 400 0 600 1 800 0 1000 1 1200 0 1400 1 1600 0 4 (default 200 (default) 1 400 0 600 1 800 0 1000 1 1200 0 1400 1 1600 Rev Page AD9516-5 ...
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... AD9516-5 Table 51. LVPECL Outputs Reg. Addr (Hex) Bit(s) Name Description 0F0 [4] OUT0 invert Sets the output polarity. [ noninverting (default). [ inverting. 0F0 [3:2] OUT0 LVPECL Sets the LVPECL output differential voltage (V differential [3] [2] voltage 0F0 [1:0] OUT0 power- LVPECL power-down modes. down ...
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... Mode Normal operation. Partial power-down, reference on; use only if there are no external load resistors. Partial power-down, reference on, safe LVPECL power-down (default). Total power-down, reference off; use only if there are no external load resistors. Rev Page AD9516-5 Output On Off Off Off Output On ...
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... AD9516-5 Table 52. LVDS/CMOS Outputs Reg. Addr (Hex) Bit(s) Name 140 [7:5] OUT6 output polarity 140 [4] OUT6 CMOS B 140 [3] OUT6 select LVDS/CMOS 140 [2:1] OUT6 LVDS output current 140 [0] OUT6 power-down 141 [7:5] OUT7 output polarity 141 [4] OUT7 CMOS B 141 [3] OUT7 select LVDS/CMOS ...
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... In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode. [ turn off the CMOS B output (default). [ turn on the CMOS B output. Select LVDS or CMOS logic levels. [ LVDS (default). [ CMOS. Rev Page AD9516-5 OUT8 (LVDS) Noninverting Noninverting (default) Noninverting Noninverting Inverting ...
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... AD9516-5 Reg. Addr (Hex) Bit(s) Name 143 [2:1] OUT9 LVDS output current 143 [0] OUT9 power-down Table 53. LVPECL Channel Dividers Reg. Addr (Hex) Bit(s) Name 190 [7:4] Divider 0 low cycles 190 [3:0] Divider 0 high cycles 191 [7] Divider 0 bypass 191 [6] Divider 0 nosync 191 ...
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... Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output stays high. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x2). Refer to LVDSCMOS channel divider function description (default: 0x0). Refer to LVDSCMOS channel divider function description (default: 0x0). Rev Page AD9516-5 ...
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... AD9516-5 Reg. Addr (Hex) Bit(s) Name 19B [7:4] Low Cycles Divider 3.2 19B [3:0] High Cycles Divider 3.2 19C [5] Bypass Divider 3.2 19C [4] Bypass Divider 3.1 19C [3] Divider 3 nosync 19C [2] Divider 3 force high 19C [1] Start High Divider 3.2 19C [0] Start High Divider 3.1 ...
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... The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is reversed; that is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. [ same as SYNC high (default). [ same as SYNC low. Rev Page AD9516-5 Divide (default) 5 ...
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... Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment.) The AD9516 features both LVPECL and LVDS outputs that provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. The input requirements of ...
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... Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9516 do not supply enough current VS to provide a full voltage swing with a low impedance resistive, far- end termination, as shown in Figure 63. The far-end termination network should match the PCB trace impedance and provide the 100Ω ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range AD9516-5BCPZ 1 −40°C to +85°C 1 AD9516-5BCPZ-REEL7 −40°C to +85°C 1 AD9516-5/PCBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 TOP VIEW BSC BSC SQ ...
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... NOTES Rev Page AD9516-5 ...
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... AD9516-5 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07972-0-1/09(0) Rev Page ...