CY7B9911-5JC Cypress Semiconductor Corp, CY7B9911-5JC Datasheet - Page 11

• Manufacturer Part Number: CY7B9911-5JC
• Description: IC CLK BUFF SKEW 8OUT 32PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr
• Series: RoboClock+™r

Specifications of CY7B9911-5JC

• Number Of Circuits: 1
• Package / Case: 32-PLCC
• Pll: Yes
• Input: TTL
• Output: TTL
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 100MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 100MHz
• Output Frequency Range: 3.75 MHz to 100 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

non-inverted outputs. The correct configuration is determined by
the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q
outputs is also skewed to compensate for varying trace delays
independent of inversion on 4Q.
Figure 7
The 3Q0 output is programmed to divide by four and is sent back
to FB. This causes the PLL to increase its frequency until the 3Q0
and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, that results in a 40 MHz waveform
at these outputs. Note that the 20 and 40 MHz clocks fall simul-
taneously and are out of phase on their rising edge. This enables
the designer to use the rising edges of the 12 frequency and 14
frequency outputs without concern for rising edge skew. The
2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed
by programming their select inputs accordingly. Note that the FS
pin is wired for 80 MHz operation because that is the frequency
of the fastest output.
Document Number: 38-07209 Rev. *F
20 MHz
Figure 8. Frequency Multiplier with Skew Connections
illustrates the PSCB configured as a clock multiplier.
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
40 MHz
20 MHz
80 MHz
Figure 8
2Q0 is fed back to the FB input and programmed for zero skew.
3Qx is programmed to divide by four. 4Qx is programmed to
divide by two. Note that the falling edges of the 4Qx and 3Qx
outputs are aligned. This enables use of the rising edges of the
12 frequency and 14 frequency without concern for skew
mismatch. The 1Qx outputs are programmed to zero skew and
are aligned with the 2Qx outputs. In this example, the FS input
is grounded to configure the device in the 15 to 30 MHz range
since the highest frequency output is running at 20 MHz.
Figure 9
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output allows the system designer to clock different subsystems
on opposite edges, without suffering from the pulse asymmetry
typical of non-ideal loading. This function enables each of the
two subsystems to clock 180 degrees out of phase, but still stay
aligned within the skew specification.
The divided outputs offer a zero delay divider for portions of the
system that divides the clock by either two or four, and still remain
within a narrow skew of the “1X” clock. Without this feature,
addition of an external divider is required and the propagation
delay of the divider adds to the skew between the different clock
signals.
These divided outputs, coupled with the Phase Locked Loop,
enable the PSCB to multiply the clock rate at the REF input by
either two or four. This mode enables the designer to distribute
a low frequency clock between various portions of the system. It
also locally multiplies the clock rate to a more suitable frequency,
maintaining the low skew characteristics of the clock driver. The
PSCB performs all of the functions described in this section at
the same time. It can multiply by two and four or divide by two
(and four) at the same time that it is shifting its outputs over a
wide range or maintaining zero skew between selected outputs.
20 MHz
Figure 9. Frequency Divider Connections
shows some of the functions that are selectable on the
demonstrates the PSCB in a clock divider application.
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
RoboClock+™
CY7B9911
10 MHz
20 MHz
5 MHz
Page 11 of 15
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