IDT5T940-30NLGI IDT, Integrated Device Technology Inc, IDT5T940-30NLGI Datasheet - Page 3

• Manufacturer Part Number: IDT5T940-30NLGI
• Description: IC CLK GENERATOR PREC 28-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of IDT5T940-30NLGI

• Input: LVDS, LVPECL, LVTTL
• Output: LVPECL
• Frequency - Max: 666.52MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN
• Frequency-max: 666.52MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5T940-30NLGI; 800-1987; IDT5T940-30NLGI

PLL BANDWIDTH SELECTION
INPUT FREQUENCY RANGE
PIN DESCRIPTION
NOTES:
1. Inputs are capable of translating the following interface standards:
2. 3-level inputs are static inputs and must be tied to V
3. Outputs can be LVPECL or LVDS.
REFIN, REFIN
CLKIN, CLKIN
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
CLK/REF
Q
Q
PLLBW
Pin Name
Single-ended 3.3V LVTTL levels
Single-ended 2.5V LVTTL levels
Differential LVPECL levels
Differential LVDS levels
PLLBW
SELmode
OUT
REG
CLK/REF
LOCK
GND
V
PD
H H
LH
HL
, Q
LL
, Q
DD
H M
M H
M M
H H
ML
LM
HL
LH
LL
[1:0]
REG
OUT
[1:0]
[1:0]
[1:0]
I/O
250KHz
65KHz
0
0
0
1MHz
4MHz
I
I
I
I
I
I
Min.
Adjustable
Adjustable
Adjustable
Adjustable
3-level
3-level
LVTTL
LVTTL
LVTTL
Type
PWR
PWR
(2)
(2)
120KHz
500KHz
2MHz
8MHz
Input Frequency Range
(1)
(1)
(3)
(3)
Max.
155.5MHz - 167MHz
19.4MHz - 20.9MHz
38.8MHz - 41.7MHz
77.7MHz - 83.4MHz
311MHz - 334MHz
622MHz - 667MHz
Automatic Detection
Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float
to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected
on the floating input.
Differential reference clock input. The reference clock input is used as an input to the PLL when CLKIN/CLKIN fails. Differential
or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL
threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the
floating input.
3 level inputs controlling PLL feedback divider ratio. Automatic detection is used if both inputs are MID.
3 level input to select output frequency range for Q
PLL Bandwidth Select Inputs (see PLL Bandwidth Selection table)
Power Down Control. Shuts off entire chip when LOW.
Differential clock output. LVPECL or LVDS outputs.
Regenerated clock output from CLKIN/CLKIN, LVPECL, or LVDS outputs.
LOW when PLL is locked to CLKIN, HIGH in all other conditions
Power Supply
Ground
reserved
reserved
DD
or GND or left floating.
Min. CLKIN/REFIN
155.52MHz
19.44MHz
19.44MHz
38.88MHz
3
OUTPUT FREQUENCY RANGE
LOCK FREQUENCY DETECTOR
when this has occurred. If CLKIN fails, the 5T940 PLL will smoothly switch
to lock to REFIN without generating any glitches on the output. The fact that
the PLL is locked to REFIN rather than CLKIN is indicated by a high state on
LOCK. When a valid input is then applied to CLKIN, the 5T940 will smoothly
switch back to locking on CLKIN, and LOCK will go low. LOCK will also switch
to high should the frequency of CLKIN drift close to the limits of the VCO tuning
range.
The 5T940 will lock to, and track, a valid CLKIN signal; LOCK will be low
SELmode
M
H
L
OUT
/Q
OUT
Description
and Q
155.5 - 166.6
Q
622 - 666.5
622 - 666.5
OUT
REG
/Q
/Q
OUT
REG
(see Output Frequency Range table)
INDUSTRIAL TEMPERATURE RANGE
regenerated CLKIN/CLKIN
regenerated CLKIN/CLKIN
155.5 - 166.6
Q
REG
/Q
REG
MHz
MHz
MHz
Unit