MB15E07SLPFV1-G-BND-6E1 Fujitsu Semiconductor America Inc, MB15E07SLPFV1-G-BND-6E1 Datasheet - Page 3
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MB15E07SLPFV1-G-BND-6E1
Manufacturer Part Number
MB15E07SLPFV1-G-BND-6E1
Description
SYNTHESIZER PLL 2.5GHZ 16SSOP
Manufacturer
Fujitsu Semiconductor America Inc
Type
Clock/Frequency Synthesizer, Prescalerr
Specifications of MB15E07SLPFV1-G-BND-6E1
Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
Yes/No
Frequency - Max
2.5GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SSOP
Frequency-max
2.5GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
865-1001-2
SSOP
PIN DESCRIPTIONS
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Pin no.
BCC
16
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
OSC
LD/fout
OSC
name
Clock
GND
Data
Xfin
Pin
V
PS
ZC
D
LE
V
fin
CC
P
R
P
O
OUT
IN
I/O
O
O
O
O
O
–
–
–
I
I
I
I
I
I
I
I
Programmable reference divider input. Connection to a TCXO.
Oscillator output.
Power supply voltage input for the charge pump.
Power supply voltage input.
Charge pump output.
Phase of the charge pump can be selected via programming of the FC bit.
Ground.
Prescaler complementary input, which should be grounded via a capacitor.
Prescaler input.
Connection to an external VCO should be done via AC coupling.
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Load enable signal input. (Open is prohibited.)
When LE is set high, the data in the shift register is transferred to a latch
according to the control bit in the serial data.
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H”; Normal mode
PS = “L”; Power saving mode
Forced high-impedance control for the charge pump (with internal pull up
resistor.)
ZC = “H”; Normal Do output.
ZC = “L”; Do becomes high impedance.
Lock detect signal output (LD)/phase comparator monitoring output (fout).
The output signal is selected via programming of the LDS bit.
LDS = “H”; outputs fout (fr/fp monitoring output)
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)
Phase comparator N-channel open drain output for an external charge
pump. Phase can be selected via programming of the FC bit.
Phase comparator CMOS output for an external charge pump. Phase can
be selected via programming of the FC bit.
Descriptions
MB15E07SL
3