MB15E07SLPFV1-G-BND-6E1 Fujitsu Semiconductor America Inc, MB15E07SLPFV1-G-BND-6E1 Datasheet - Page 8
![SYNTHESIZER PLL 2.5GHZ 16SSOP](/photos/6/56/65612/mb15e03slpfv1-g-bnd-6e1_sml.jpg)
MB15E07SLPFV1-G-BND-6E1
Manufacturer Part Number
MB15E07SLPFV1-G-BND-6E1
Description
SYNTHESIZER PLL 2.5GHZ 16SSOP
Manufacturer
Fujitsu Semiconductor America Inc
Type
Clock/Frequency Synthesizer, Prescalerr
Specifications of MB15E07SLPFV1-G-BND-6E1
Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
Yes/No
Frequency - Max
2.5GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SSOP
Frequency-max
2.5GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
865-1001-2
8
MB15E07SL
1. Pulse Swallow Function
2. Serial Data Input
Table 1. Control Bit
(1) Shift Register Configuration
LSB
FUNCTIONAL DESCRIPTION
The divide ratio can be calculated using the following equation:
f
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data as follows:
VCO
C
N
1
T
CNT
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383)
SW
FC
LDS
CS
Note: Start data input with MSB first.
= [(M
Programmable Reference Counter
Control bit (CNT)
f
N
A
f
R
M : Preset divide ratio of modulus prescaler (32 or 64)
R
2
1
VCO
OSC
: Output frequency of external voltage controlled oscillator (VCO)
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
N) + A]
R
3
2
H
: Control bit
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
: Phase control bit for the phase comparator
: LD/f
: Charge pump current select bit
L
R
OUT
4
3
f
signal select bit
OSC
R
5
4
R (A < N)
R
6
5
For the programmable reference divider
For the programmable divider
R
7
6
R
8
7
Data Flow
R
9
8
10
R
9
Destination of serial data
11
10
R
12
11
R
A
13
12
R
127)
14
13
R
15
14
R
SW FC LDS CS
16
17
[Table 1]
[Table 2]
[Table 5]
[Table 8]
[Table 7]
[Table 6]
18
MSB
19