MB15E07SLPFV1-G-BND-6E1 Fujitsu Semiconductor America Inc, MB15E07SLPFV1-G-BND-6E1 Datasheet - Page 3
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MB15E07SLPFV1-G-BND-6E1
Manufacturer Part Number
MB15E07SLPFV1-G-BND-6E1
Description
SYNTHESIZER PLL 2.5GHZ 16SSOP
Manufacturer
Fujitsu Semiconductor America Inc
Type
Clock/Frequency Synthesizer, Prescalerr
Specifications of MB15E07SLPFV1-G-BND-6E1
Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
Yes/No
Frequency - Max
2.5GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SSOP
Frequency-max
2.5GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
865-1001-2
Single PLL Frequency Synthesizers with On-Chip Prescalers
Pin Descriptions
2
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Fujitsu Microelectronics, Inc.
Pin No.
BCC
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin Name
OSC
OSC
V
V
Do
GND
Xfin
fin
Clock
Data
LE
PS
ZC
LD/f
OSC
P
CC
P
R
OSC
GND
OUT
IN
OUT
Xfin
V
OUT
D
V
fin
CC
IN
O
P
I/O
1
2
3
4
5
6
7
8
—
—
—
O
O
O
O
O
I
I
I
I
I
I
I
I
VIEW
TOP
Programmable reference divider input
Oscillator input connection to a TCXO
Oscillator output
Power supply voltage input for the charge pump
Power supply voltage input
Charge pump output
Phase of the charge pump can be selected via programming of the FC bit.
Ground
Prescaler complementary input which should be grounded via a capacitor.
Prescaler input
Connection to an external VCO should be done via AC coupling.
Clock input for 19-bit shift register
Data is shifted into shift register on rising edge of the clock. (Open is prohibited.)
Serial data input using binary code
Last bit of data is a control bit. (Open is prohibited.)
Load enable signal input. (Open is prohibited.)
When LE is set high, data in the shift register is transferred to a latch according to control bit in the serial data.
Power-saving mode control. Pin must be set at “L” at Power-ON. (Open is prohibited.)
PS = “H” sets normal mode. PS = “L” sets power-saving mode.
Forced high-impedance control for the charge pump (with internal pull up resistor)
ZC = “H” sets normal Do output. ZC = “L”; Do becomes high impedance.
Lock detect signal output (LD)/phase comparator monitoring output (f
The output signal is selected via programming of the LDS bit.
LDS = “H” outputs f
LDS = “L” outputs LD (“H” = locked state, “L” = unlocked state).
Phase comparator N-channel open drain output for an external charge pump. Phase can be selected via programming
of the FC bit.
Phase comparator CMOS output for an external charge pump. Phase can be selected via programming of the FC bit.
16
15
14
13
12
11
10
9
LD/f
ZC
PS
LE
Data
Clock
R
P
OUT
OUT
(fr/fp monitoring output).
OSC
GND
Xfin
V
OUT
D
V
CC
O
P
Descriptions
1
2
3
4
5
6
OSC
fin Clock
16
VIEW
7
TOP
IN
15
8
R
14
13
12
11
10
9
OUT
)
LD f
ZC
PS
LE
Data
P
OUT