ADF4118BRUZ Analog Devices Inc, ADF4118BRUZ Datasheet - Page 19

• Manufacturer Part Number: ADF4118BRUZ
• Description: IC PLL FREQ SYNTHESIZER 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4118BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 3GHz
• Pll Type: Frequency Synthesis
• Frequency: 3GHz
• Supply Current: 6.5mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Number Of Elements: 1
• Pll Input Freq (min): 5MHz
• Pll Input Freq (max): 3GHz
• Operating Supply Voltage (typ): 3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: Up to 200MHz
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4118EBZ1 - BOARD EVAL FOR ADF4118
• Lead Free Status / Rohs Status: Compliant

FUNCTION LATCH
With C2 and C1 set to 1 and 0, respectively, the on-chip
function latch is programmed. Figure 33 shows the input data
format for programming the function latch.
COUNTER RESET
DB2 (F1) is the counter reset bit. When this bit is set to 1, the R
counter, A counter, and B counter are reset. For normal operation,
this bit should be set to 0. On power-up, the F1 bit needs to be
disabled, for the N counter to resume counting in “close”
alignment with the R counter. (The maximum error is one
prescaler cycle.)
POWER-DOWN
DB3 (PD1) and DB19 (PD2) on the ADF411x family provide
programmable power-down modes. They are enabled by the
CE pin.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2 and PD1.
In programmed asynchronous power-down, the device powers
down immediately after latching a 1 into the PD1 bit, with the
condition that PD2 is loaded with a 0.
In programmed synchronous power-down, the device power-
down is gated by the charge pump to prevent unwanted
frequency jumps. Once power-down is enabled by writing a 1
into the PD1 bit (on condition that a 1 is also loaded to PD2),
the device goes into power-down after the first successive
charge pump event.
When a power-down is activated (either synchronous or
asynchronous mode including CE pin-activated power-down),
the following events occur:
•
•
•
•
•
•
•
MUXOUT CONTROL
The on-chip multiplexer is controlled by DB6 (M3), DB5 (M2),
and DB4 (M1) on the ADF411x family. Figure 33 shows the
truth table.
PHASE DETECTOR POLARITY
DB7 (F2) of the function latch sets the phase detector polarity.
When the VCO characteristics are positive, DB7 should be set
to 1. When they are negative, it should be set to 0.
All active dc current paths are removed.
The R counter, N counter, and timeout counter are forced
to their load state conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RF
The oscillator input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.
IN
input is debiased.
Rev. D | Page 19 of 28
CHARGE PUMP THREE-STATE
The DB8 (F3) bit puts the charge pump into three-state mode
when programmed to 1. It should be set to 0 for normal operation.
FASTLOCK ENABLE BIT
DB9 (F4) of the function latch is the fastlock enable bit. Fastlock
is enabled only when DB9 is set to 1.
FASTLOCK MODE BIT
DB11 (F6) of the function latch is the fastlock mode bit. When
fastlock is enabled, this bit determines which fastlock mode is
used. If the fastlock mode bit is 0, Fastlock Mode 1 is selected; if
the fastlock mode bit is 1, Fastlock Mode 2 is selected.
If fastlock is not enabled (DB9 = 0), DB11 (ADF4116)
determines the state of the FL
that programmed to DB11.
Fastlock Mode 1
In the ADF411x family, the output level of FL
to a low state, and the charge pump current is switched to the
high value (1 mA). FL
filter and to ensure stability while in fastlock by altering the
loop bandwidth.
The device enters fastlock by having a 1 written to the CP Gain
bit in the N register. The device exits fastlock by having a 0
written to the CP Gain bit in the N register.
Fastlock Mode 2
In the ADF411x family, the output level of FL
to a low state, and the charge pump current is switched to the
high value (1 mA). FL
filter and to ensure stability while in fastlock by altering the
loop bandwidth.
The device enters fastlock by having a 1 written to the CP gain
bit in the N register. The device exits fastlock under the control
of the timer counter. After the timeout period determined by
the value in TC4 to TC1, the CP Gain bit in the N register is
automatically reset to 0, and the device reverts to normal mode
instead of fastlock.
TIMER COUNTER CONTROL
In the ADF411x family, the user has the option of switching
between two charge pump current values to speed up locking to
a new frequency.
When using the fastlock feature with the ADF411x family, the
following should be noted:
•
The user must make sure that fastlock is enabled. Set DB9
to 1. The user must also choose which fastlock mode to use.
ADF4116/ADF4117/ADF4118
O
O
is used to switch a resistor in the loop
is used to switch a resistor in the loop
O
output. FL
O
state is the same as
O
O
is programmed
is programmed