IDTCSP2510DPG IDT, Integrated Device Technology Inc, IDTCSP2510DPG Datasheet

IDTCSP2510DPG

Manufacturer Part Number

IDTCSP2510DPG

Description

IC CLK DVR PLL ZDB 1:10 24TSSOP

Manufacturer

IDT, Integrated Device Technology Inc

Type

Driver, PLL, Zero Delay Bufferr

Datasheet

1.IDTCSP2510DPGG.pdf (9 pages)

Specifications of IDTCSP2510DPG

Pll

Yes with Bypass

Input

Clock

Output

Clock

Number Of Circuits

Ratio - Input:output

1:10

Differential - Input:output

No/No

Frequency - Max

175MHz

Divider/multiplier

No/No

Voltage - Supply

3 V ~ 3.6 V

Operating Temperature

0°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

24-TSSOP

Frequency-max

175MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

CSP2510DPG

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

IDTCSP2510DPGG

Manufacturer:

Intersil

Quantity:

378

Current page: 1 of 9
Download datasheet (77Kb)

FEATURES:

• Phase-Lock Loop Clock Distribution for Synchronous DRAM

• Distributes one clock input to one bank of ten outputs

• Output enable bank control

• External feedback (FBIN) pin is used to synchronize the

• No external RC network required for PLL loop stability

• Operates at 3.3V V

• tpd Phase Error at 166MHz: < ±150ps

• Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz

• Spread Spectrum Compatible

• Operating frequency 50MHz to 175MHz

• Available in 24-Pin TSSOP package

APPLICATIONS:

• SDRAM Modules

• PC Motherboards

• Workstations

0º º º º º C TO 85º º º º º C TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDTCSP2510D

3.3V PHASE-LOCK LOOP CLOCK DRIVER

Applications

outputs to the clock input signal

2001 Integrated Device Technology, Inc.

FUNCTIONAL BLOCK DIAGRAM

FBIN

CLK

3.3V PHASE-LOCK LOOP

CLOCK DRIVER

ZERO DELAY BUFFER

PLL

DESCRIPTION:

loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency

and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CSP2510D

operates at 3.3V.

Output signal duty cycles are adjusted to 50 percent, independent of the duty

cycle at CLK. The outputs can be enabled or disabled via the control G input.

When the G input is high, the outputs switch in phase and frequency with

CLK; when the G input is low, the outputs are disabled to the logic-low state.

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as

following any changes to the PLL reference or feedback signals. The PLL

can be bypassed for the test purposes by strapping AV

is also available (on special order) in Industrial temperature range (-40°C

to +85°C). See ordering information for details.

The CSP2510D is a high performance, low-skew, low-jitter, phase-lock

One bank of ten outputs provide low-skew, low-jitter copies of CLK.

Unlike many products containing PLLs, the CSP2510D does not require

Because it is based on PLL circuitry, the CSP2510D requires a

The CSP2510D is specified for operation from 0°C to +85°C. This device

FBOUT

C TO 85

C TEMPERATURE RANGE

IDTCSP2510D

OCTOBER 2001

to ground.

DSC-5874/3

Related parts for IDTCSP2510DPG

IDTCSP2510DPG Summary of contents

Page 1

IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER FEATURES: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to ...

Page 2

IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER PIN CONFIGURATION AGND GND 7 GND FBOUT 12 TSSOP TOP VIEW RECOMMENDED OPERATING CONDITIONS ...

Page 3

IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER PIN DESCRIPTION Terminal Name No. Type CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CSP2510D clock driver. CLK is used to provide the reference signal to the ...

Page 4

IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERA- TURE RANGE (1) Symbol Description V Input Clamp Voltage IK V Input HIGH Level IH V Input LOW Level IL V HIGH Level Output Voltage OH V ...

Page 5

IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C Parameter (2) From (Input) t error 100MHz < CLK↑ < 166MHz PHASE (3) t error – jitter CLK↑ = 166MHz PHASE ...

Page 6

IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER PARAMETER MEASUREMENT INFORMATION From Output Under Test C = 30pF L Y CLK C = 30pF L CSP2510D F BOUT F BIN C F PCB TRACE NOTES: 1. All inputs pulses are supplied by ...

Page 7

IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER TYPICAL CHARACTERISTICS 200 150 100 -50 -100 -150 -200 Phase Error vs Clock Frequency AV and ...

Page 8

IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER TYPICAL CHARACTERISTICS (CONT 140 120 100 Cycle-to-Cycle 0 50 Output Duty Cycle vs Clock Frequency AV and V ...

Page 9

IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER ORDERING INFORMATION IDTCSP XXXXX XX Device Type Package CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X Process Blank I PG 2510D for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 9 ...

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