MPC9653AAC/W IDT, Integrated Device Technology Inc, MPC9653AAC/W Datasheet

MPC9653AAC/W

Manufacturer Part Number

MPC9653AAC/W

Description

IC PLL CLK GEN 1:8 3.3V 32-LQFP

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Generatorr

Datasheet

1.MPC9653AACW.pdf (10 pages)

Specifications of MPC9653AAC/W

Pll

Yes with Bypass

Input

LVPECL

Output

LVCMOS

Number Of Circuits

Ratio - Input:output

1:8

Differential - Input:output

Yes/No

Frequency - Max

125MHz

Divider/multiplier

Yes/No

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

32-LQFP

Frequency-max

125MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

MPC9653AAC/W

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

3.3 V 1:8 LVCMOS PLL Clock

Generator

Freescale Semiconductor, Inc.

TECHNICAL DATA

3.3 V 1:8 LVCMOS PLL Clock

Generator

zero-delay buffer targeted for high performance low-skew clock distribution in

mid-range to high-performance telecom, networking and computing

applications. With output frequencies up to 125 MHz and output skews less

than 150 ps the device meets the needs of the most demanding clock

applications.

Features

•

Functional Description

MPC9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With

the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency

range of 25 to 62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8)

and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The

internal VCO of the MPC9653A is running at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock

in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F

zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass config-

urations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can

be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock

due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, en-

abling the PLL to recover to normal operation.

MOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For

series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an effective fanout

of 1:16. The device is packaged in a 7x7 mm

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and

The MPC9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as a

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected

The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVC-

1:8 PLL based low-voltage clock generator

32-lead Pb-free Package Available

Supports zero-delay operation

3.3 V power supply

Generates clock signals up to 125 MHz

PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz

Maximum output skew of 150 ps

Differential LVPECL reference clock input

External PLL feedback

Drives up to 16 clock lines

32-lead LQFP packaging

Ambient temperature range 0°C to +70°C

Pin and function compatible to the MPC953 and MPC9653

32-lead LQFP package.

PLL CLOCK GENERATOR

32-LEAD LQFP PACKAGE

MPC9653A

3.3 V LVCMOS 1:8

LOW VOLTAGE

CASE 873A-03

ref

FA SUFFIX

AC SUFFIX

= 36.25 MHz.

Order number: MPC9653A

DATA SHEET

MPC9653A

Rev 3, 08/2004

MPC9653A

529

Related parts for MPC9653AAC/W

MPC9653AAC/W Summary of contents

Page 1

Freescale Semiconductor, Inc. TECHNICAL DATA 3.3 V 1:8 LVCMOS PLL Clock 3.3 V 1:8 LVCMOS PLL Clock Generator Generator The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock ...

Page 2

MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator MPC9653A V 2⋅25 k PCLK PCLK FB_IN V CC 3⋅25 k PLL_EN VCO_SEL BYPASS MR/ GND V QFB GND PLL_EN BYPASS VCO_SEL IDT™ 3.3 V 1:8 ...

Page 3

MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator Table 1. Pin Configuration Pin I/O Type PCLK, PCLK Input LVPECL FB_IN Input LVCMOS VCO_SEL Input LVCMOS BYPASS Input LVCMOS PLL_EN Input LVCMOS MR/OE Input LVCMOS Q0–7 Output LVCMOS QFB Output LVCMOS ...

Page 4

MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator MPC9653A Table 3. General Specifications Symbol Characteristics V Output Termination Voltage TT MM ESD Protection (Machine Model) HBM ESD Protection (Human Body Model) LU Latch-Up Immunity C Power Dissipation Capacitance PD C ...

Page 5

MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator Table 6. AC Characteristics (V = 3.3 V ± 5 Symbol Characteristics f Input Reference Frequency REF PLL Mode, External Feedback Input reference frequency in PLL bypass mode f VCO ...

Page 6

MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator MPC9653A Programming the MPC9653A The MPC9653A supports output clock frequencies from 25 to 125 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback ...

Page 7

MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator Calculation of Part-to-Part Skew The MPC9653A zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9653As ...

Page 8

MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator MPC9653A MPC9653A OUTPUT BUFFER = 36 Ω Ω IN MPC9653A OUTPUT = 36 Ω BUFFER 14 Ω Ω Figure 6. Single versus ...

Page 9

MPC9653A 3.3 V 1:8 LVCMOS PLL Clock Generator t SK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 10. Output-to-Output Skew ...

Page 10

MPC9653A PART NUMBERS 3.3 V 1:8 LVCMOS PLL Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver ...

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