MPC9653AAC/W IDT, Integrated Device Technology Inc, MPC9653AAC/W Datasheet - Page 8

• Manufacturer Part Number: MPC9653AAC/W
• Description: IC PLL CLK GEN 1:8 3.3V 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9653AAC/W

• Pll: Yes with Bypass
• Input: LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
of an output driving a single line versus two lines. In both cases
the drive capability of the MPC9653A output buffer is more than
sufficient to drive 50 Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta of
only 43 ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the
MPC9653A. The output waveform in
the waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
36 Ω series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
reflection coefficient, to 2.6 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in
this case 4.0 ns).
536
At the load end the voltage will double, due to the near unity
IN
IN
The waveform plots in
Figure 6. Single versus Dual Transmission Lines
V
Z
R
R
V
MPC9653A
MPC9653A
OUTPUT
BUFFER
OUTPUT
0
BUFFER
L
L
S
0
14 Ω
14 Ω
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 ÷ (18 + 14 + 25)
= 1.31 V
S
(Z
0
÷ (R
Pulse Generator
R
R
R
Differential
S
Z = 50 Ω
S
S
Figure 7
= 36 Ω
= 36 Ω
= 36 Ω
S
+ R
0
+ Z
show the simulation results
Figure 7
0
Z
Z
))
Z
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
Z
Figure 9. MPC9653A AC Test Reference
O
V
shows a step in
= 50 Ω
TT
R
T
= 50 Ω
OutB1
OutA
OutB0
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
8
MPC9653A DUT
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
Figure
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 8. Optimized Dual Line Termination
8, should be used. In this case the series terminating
Figure 7. Single versus Dual Waveforms
MPC9653A
OUTPUT
BUFFER
14 Ω
t
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
2
D
Z
= 3.8956
OutA
O
In
= 50 Ω
4
R
T
25 Ω = 25 Ω
= 50 Ω
R
R
S
S
6
= 22 Ω
= 22 Ω
TIME (ns)
t
D
V
= 3.9386
OutB
TT
8
Z
Z
O
O
= 50 Ω
= 50 Ω
10
12
NETCOM
14
MPC9653A