MPC9653AACR2/W IDT, Integrated Device Technology Inc, MPC9653AACR2/W Datasheet - Page 7

• Manufacturer Part Number: MPC9653AACR2/W
• Description: IC PLL CLK GEN 1:8 3.3V 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9653AACR2/W

• Pll: Yes with Bypass
• Input: LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
Calculation of Part-to-Part Skew
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9653As are connected together, the maximum overall
timing uncertainty from the common PCLK input to any output
is:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from
Table 8. Confidence Factor CF
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Figure 4. MPC9653A Maximum Device-to-Device Skew
The MPC9653A zero delay buffer supports applications
This maximum timing uncertainty consist of 4 components:
Due to the statistical nature of I/O jitter a RMS value (1 σ) is
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
CF
t
SK(PP)
Any Q
Any Q
PCLK
QFB
QFB
Max. skew
Common
Device 1
Device 1
Device 2
Device2
= t
Probability of clock edge within the distribution
(
∅
)
+ t
SK(O)
Table
t
JIT(∅)
+ t
8.
—t(ý)
+t
PD, LINE(FB)
SK(O)
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
+t
t
(∅)
SK(PP)
t
JIT(∅)
+ t
JIT(
t
PD,LINE(FB)
+t
∅
SK(O)
)
⋅ CF
7
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter
confidence factor of 99.7% (± 3σ) is assumed, resulting in a
worst case timing uncertainty from input to any output of
–197 ps to 297 ps (at 125 MHz reference frequency) relative to
PCLK:
can be used for a more precise timing performance analysis.
Driving Transmission Lines
speed signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20 Ω the drivers can drive
either parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to
Motorola application note AN1091. In most high performance
clock networks point-to-point distribution of signals is the
method of choice. In a point-to-point scheme either series
terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of
the line with a 50 Ω resistance to V
thus only a single terminated line can be driven by each output
of the MPC9653A clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines.
driving a single series terminated line versus two series
terminated lines in parallel. When taken to its extreme the
fanout of the MPC9653A clock driver is effectively doubled due
to its capability to drive multiple lines.
The feedback trace delay is determined by the board layout
Due to the frequency dependence of the I/O jitter,
The MPC9653A clock driver was designed to drive high
This technique draws a fairly high level of DC current and
t
t
SK(PP)
SK(PP)
30
20
10
Figure 5. Maximum I/O Jitter versus Frequency
0
25
= [-17ps...117ps] + [-150ps...150ps] +
= [-197ps...297ps] + t
35
FB = ÷ 8
45
[(10ps @ -3)...(10ps @ 3)] + t
55
65
75
Figure
PD, LINE(FB)
CC
85
Reference Frequency [MHz]
÷ 2.
5, illustrates an output
95
FB = ÷ 4
105
MPC9653A
PD, LINE(FB)
115
Figure
NETCOM
125
MPC9653A
535
5,