MPC93R51ACR2 IDT, Integrated Device Technology Inc, MPC93R51ACR2 Datasheet - Page 10

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MPC93R51ACR2

Manufacturer Part Number
MPC93R51ACR2
Description
IC PLL CLK DRIVER LV 32-LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet

Specifications of MPC93R51ACR2

Pll
Yes with Bypass
Input
LVCMOS, LVPECL
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
2:9
Differential - Input:output
Yes/No
Frequency - Max
240MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
240MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC93R51ACR2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93R51
Low Voltage PLL Clock Driver
10
MPC93R51
PCLK
PCLK
Ext_FB
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
The deviation in t
in a random sample of cycles.
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
TCLK
(PCLK)
Figure 12. Propagation Delay (t
Ext_FB
Figure 14. Output Duty Cycle (DC)
Figure 16. Cycle-to-Cycle Jitter
0
Offset) Test Reference
for a controlled edge with respect to a t
t
T
P
N
Figure 18. I/O Jitter
t
(∅)
T
T
0
N+1
DC = t
V
CMR
P
T
/T
JIT(∅)
0
T
x 100%
JIT(CC)
PD
= |T
, Static Phase
= |T
0
–T
N
1
–T
mean|
N+1
V
V
GND
CC
CC
V
V
V
GND
|
0
CC
CC
CMR
÷ 2
mean
÷ 2
10
TCLK
Ext_FB
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles.
Figure 13. Propagation Delay (t
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
Figure 19. Transition Time Test Reference
Figure 15. Output-to-Output Skew t
t
F
T
0
Figure 17. Period Jitter
t
(∅)
Advanced Clock Drivers Devices
t
SK(O)
Freescale Semiconductor
T
JIT(PER)
PD
) Test Reference
t
R
= |T
V
CC
N
–1/f
0.55
=3.3 V
2.4
SK(O)
0
|
V
V
GND
V
V
GND
V
V
GND
V
V
GND
CC
CC
CC
CC
CC
CC
CC
CC
÷ 2
÷ 2
NETCOM
÷ 2
÷ 2
MPC93R51

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