MPC93R51ACR2 IDT, Integrated Device Technology Inc, MPC93R51ACR2 Datasheet - Page 5

• Manufacturer Part Number: MPC93R51ACR2
• Description: IC PLL CLK DRIVER LV 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC93R51ACR2

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: Yes/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93R51
Low Voltage PLL Clock Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 6. AC Characteristics (V
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. The PLL will be unstable with a divide by 2 feedback rati,o
3. V
4. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t
Symbol
V
t
t
t
t
JIT(PER)
PLZ, HZ
PZL, ZH
t
JIT(CC)
t
t
f
CMR
f
f
r
t
JIT(∅)
refDC
LOCK
and the input swing lies within the V
are within the specified range.
V
VCO
MAX
, t
t
sk(o)
DC
t
BW
f
r
(∅)
ref
, t
CMR
PP
f
(4)
f
(3)
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input Frequency
VCO Frequency
Maximum Output Frequency
Reference Input Duty Cycle
Peak-to-Peak Input Voltage
Common Mode Range
TCLK Input Rise/Fall Time
Propagation Delay (static phase offset)
Output-to-Output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
PLL closed loop bandwidth
Cycle-to-cycle jitter
Single Output Frequency Configuration
Period Jitter
Single Output Frequency Configuration
I/O Phase Jitter
Maximum PLL Lock Time
Characteristics
(2)
CC
= 3.3 V ± 5%, T
PCLK to EXT_FB
TCLK to EXT_FB
PP
Static test mode
2
100 – 240 MHz
(AC) specification. Violation of V
50 – 120 MHz
PCLK, PCLK
PCLK, PCLK
÷ 4 feedback
÷ 8 feedback
÷ 4 feedback
÷ 8 feedback
÷ 4 feedback
÷ 4 feedback
25 – 60 MHz
÷ 2 output
÷ 4 output
÷ 8 output
A
= 0° to 70°C)
48.75
47.5
Min
+25
200
100
500
1.2
-50
0.1
50
25
50
25
25
45
0
5
TT.
(1)
CMR
3.0 – 9.5
1.2 – 2.1
4.0 – 17
Typ
or V
8.0
50
50
50
10
PP
impacts static phase offset t
V
51.75
CC
1000
+150
+325
Max
52.5
120
300
480
240
120
150
1.0
1.0
7.0
6.0
1.0
60
60
75
55
22
15
–0.9
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
mV
ms
%
ns
ps
ps
ps
%
%
%
ns
ns
ns
ps
ps
ps
V
(∅)
, can only be guaranteed if t
PLL_EN = 1
PLL_EN = 1
PLL_EN = 0
LVPECL
LVPECL
0.8 to 2.0 V
0.55 to 2.4 V
–3 db point of
PLL transfer characteristic
RMS value
RMS value
RMS value
PLL locked
PLL locked
(∅)
.
Condition
MPC93R51
CMR
range
NETCOM
MPC93R51
r
/t
5
f