CY2304SXC-1 Cypress Semiconductor Corp, CY2304SXC-1 Datasheet

IC CLK ZDB 4OUT 133MHZ 8SOIC

CY2304SXC-1

Manufacturer Part Number
CY2304SXC-1
Description
IC CLK ZDB 4OUT 133MHZ 8SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Datasheet

Specifications of CY2304SXC-1

Number Of Circuits
1
Package / Case
8-SOIC (3.9mm Width)
Pll
Yes
Input
Clock
Output
Clock
Ratio - Input:output
1:4
Differential - Input:output
No/No
Frequency - Max
133.3MHz
Divider/multiplier
No/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
133MHz
Output Frequency Range
10 MHz to 133.3 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Number Of Elements
1
Supply Current
45mA
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
SOIC
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2192-5
CY2304SXC-1

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY2304SXC-1
Quantity:
153
Part Number:
CY2304SXC-1T
Manufacturer:
CY
Quantity:
158
Part Number:
CY2304SXC-1T
Manufacturer:
CY
Quantity:
1 000
Part Number:
CY2304SXC-1T
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
3.3 V Zero Delay Buffer
Features
Functional Description
The CY2304 is a 3.3 V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip phase-locked loop (PLL) that locks to an
input clock presented on the REF pin. The PLL feedback is
required to be driven into the FBK pin, and can be obtained from
Table 1. Available Configurations
Cypress Semiconductor Corporation
Document Number: 38-07247 Rev. *J
Logic Block Diagram
Zero input-output propagation delay, adjustable by capacitive
load on FBK input
Multiple configurations
Multiple low-skew outputs
10 MHz to 133 MHz operating range
90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz
Space-saving 8-pin 150-mil small outline integrated circuit
(SOIC) package
3.3 V operation
Industrial temperature available
CY2304-1
CY2304-2
CY2304-2
Device
REF
Bank A or B
FBK from
Bank A
Bank B
198 Champion Court
PLL
Bank A Frequency
one of the outputs. The input-to-output skew is guaranteed to be
less than 250 ps, and output-to-output skew is guaranteed to be
less than 200 ps.
The CY2304 has two banks of two outputs each.
The CY2304 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
25 A of current draw.
Multiple CY2304 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 500 ps.
The CY2304 is available in two different configurations, as
shown in
output frequencies equal the reference if there is no counter in
the feedback path.
The CY2304–2 allows the user to obtain Ref and 1/2x or 2x
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the feedback
pin.
2 × Reference
Reference
Reference
/2
Table
San Jose
Extra Divider (-2)
3.3 V Zero Delay Buffer
1. The CY2304–1 is the base part, where the
,
CA 95134-1709
CLKA1
CLKB2
CLKB1
CLKA2
FBK
Bank B Frequency
Reference/2
Reference
Reference
Revised March 24, 2011
408-943-2600
CY2304
[+] Feedback

Related parts for CY2304SXC-1

CY2304SXC-1 Summary of contents

Page 1

... CY2304-1 Bank CY2304-2 Bank A CY2304-2 Bank B Cypress Semiconductor Corporation Document Number: 38-07247 Rev. *J 3.3 V Zero Delay Buffer one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. The CY2304 has two banks of two outputs each. ...

Page 2

... Zero Delay and Skew Control .......................................... 4 Maximum Ratings ............................................................. 5 Operating Conditions for CY2304SXC Commercial Temperature Devices ....................................................... 5 Electrical Characteristics for CY2304SXC Commercial Temperature Devices ....................................................... 5 Switching Characteristics for CY2304SXC Commercial Temperature Devices ....................................................... 6 Electrical Characteristics for CY2304SXI Industrial Temperature Devices ....................................................... 7 Operating Conditions for CY2304SXI Industrial Temperature Devices ....................................................... 7 Document Number: 38-07247 Rev ...

Page 3

Pinout l Table 2. Pin Definitions - 8-pin SOIC Pin Signal [1] 1 REF 2 CLKA1 3 CLKA2 4 GND 5 CLKB1 6 CLKB2 FBK Notes 1. Weak pull-down. 2. Weak pull-down on all outputs. Document ...

Page 4

Zero Delay and Skew Control Figure 2. REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins To close the feedback loop of the CY2304, the FBK pin can be driven from any of the ...

Page 5

... Load capacitance (below 100 MHz) L Load capacitance (from 100 MHz to 133 MHz) C [3] Input capacitance IN t Power-up time for all (power ramps must be monotonic) Electrical Characteristics for CY2304SXC Commercial Temperature Devices Parameter Description V Input LOW voltage IL V Input HIGH voltage IH I Input LOW current IL ...

Page 6

... Switching Characteristics for CY2304SXC Commercial Temperature Devices [5] Name Parameter t Output frequency 1 t Output frequency 1 t [6] t Duty cycle = (–1,–2) t [6] t Duty cycle = (–2) t [6] t Duty cycle = (–1,–2) t [6] Rise time 3 (–1, –2) [6] t Rise time 3 (– ...

Page 7

Operating Conditions for CY2304SXI Industrial Temperature Devices Parameter V Supply voltage DD T Operating temperature (ambient temperature Load capacitance (below 100 MHz) L Load capacitance (from 100 MHz to 133 MHz) C Input capacitance IN Electrical Characteristics for ...

Page 8

Switching Characteristics for CY2304SXI Industrial Temperature Devices [8] Parameter Name t Output frequency 1 t Output frequency 1 t [9] t Duty cycle = (–1,–2) t [9] t Duty cycle = (–2) ...

Page 9

Switching Waveforms OUTPUT OUTPUT OUTPUT INPUT FBK FBK, Device 1 FBK, Device 2 Document Number: 38-07247 Rev. *J Figure 2. Duty Cycle Timing 1.4 V 1.4 V 1.4 V Figure 3. All Outputs Rise/Fall Time 2.0 ...

Page 10

Document Number: 38-07247 Rev. *J Figure 7. Test Circuit # CLK OUTPUTS C LOAD V DD GND GND Test circuit for all parameters CY2304 OUT Page [+] Feedback ...

Page 11

... SOIC CY2304SXI–1 8-pin 150-mil SOIC - Tape and Reel CY2304SXI–1T 8-pin 150-mil SOIC CY2304SXC–2 8-pin 150-mil SOIC - Tape and Reel CY2304SXC–2T 8-pin 150-mil SOIC CY2304SXI–2 8-pin 150-mil SOIC - Tape and Reel CY2304SXI–2T Ordering Code Definitions CY ...

Page 12

Package Drawing and Dimensions Document Number: 38-07247 Rev. *J Figure 8. 8-pin (150-Mil) SOIC S8 CY2304 51-85066 *D Page [+] Feedback ...

Page 13

Acronyms Acronym Description PCI Personal computer interconnect PLL Phase locked loop SDRAM Synchronous dynamic random access memory SOIC Small outline integrated circuit TSSOP Thin small outline package ZDB Zero delay buffer Document Number: 38-07247 Rev. *J Document Conventions Units of ...

Page 14

... Removed parts CY2304SC-1, CY2304SC-1T,CY2304SC-2,CY2304SC-2T,CY2304SI-1,CY2304SI-1T from the ordering information table. Updated Package Diagram. 10/27/2010 Corrected part number in all table titles (pages from CY2304SC-X and CY2304SI-X to CY2304SXC and CY2304SXI. Removed “except t ” from Figure 7 8 02/04/2011 Updated in new template. 03/24/2011 Added duty cycle spec for 83.0 MHz output condition. ...

Page 15

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

Related keywords