MPC9600AE IDT, Integrated Device Technology Inc, MPC9600AE Datasheet - Page 8

• Manufacturer Part Number: MPC9600AE
• Description: IC PLL CLK DRIVER LV 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MPC9600AE

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:22
• Differential - Input:output: Yes/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Frequency-max: 200MHz
• Number Of Elements: 1
• Supply Current: 5mA
• Pll Input Freq (min): 16.67MHz
• Pll Input Freq (max): 50MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Output Frequency Range: 50 to 200MHz
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
f
MPC9600
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
ref
= 20.833 MHz
Table 9. Typical and Maximum Period Jitter Specification
Table 10. Typical and Maximum Cycle-to-Cycle Jitter Specification
All output banks in ÷ 2 or ÷ 4 divider configuration
Mixed ÷ 2/÷ 4 divider configurations
All output banks in ÷ 2 or ÷ 4 divider configuration
Mixed ÷2/÷ 4 divider configurations
Frequency Range
1. In this configuration, all MPC9600 outputs generate the same clock frequency. See
2. Multiple frequency generation. Jitter data are specified for each output divider separately. See
1. In this configuration, all MPC9600 outputs generate the same clock frequency.
2. Multiple frequency generation. Jitter data are specified for each output divider separately.
QA outputs
QB outputs
QC outputs
Figure 3. Configuration for 126 MHz Clocks
÷ 2 (FSELA = 0 and FESLB = 0 and FSELC = 0)
÷ 4 (FSELA = 1 and FESLB = 1 and FSELC = 1)
÷ 2 (FSELA = 0 and FESLB = 0 and FSELC = 0)
÷ 4 (FSELA = 1 and FESLB = 1 and FSELC = 1)
Input
1
0
0
0
for output banks in ÷ 2 divider configurations
for output banks in ÷ 4 divider configurations
for output banks in ÷ 2 divider configurations
for output banks in ÷ 4 divider configurations
CCLK
FB_IN
FSEL_FB
FSELA
FSELB
FSELC
20.833 MHz (Feedback)
Device Configuration
Device Configuration
MPC9600
16.67 MHz
100 MHz
100 MHz
100 MHz
Min
QA0–6
QB0–6
QC0–6
QFB
(2)
(2)
7
7
7
33.33 MHz
200 MHz
200 MHz
200 MHz
Max
125 MHz
125 MHz
125 MHz
(1)
(1)
Typ
Typ
150
25
20
80
25
40
40
30
QA0 to QA6
QA0 to QA6
8
Max
Max
130
110
250
110
50
70
70
90
Figure 4. Configuration for 133.3/66.67 MHz Clocks
f
ref
= 33.33 MHz
Frequency Range
Figure 3
QC outputs
QA outputs
QB outputs
Typ
100
Typ
120
200
120
Input
50
50
60
80
QB0 to QB6
QB0 to QB6
0
0
1
1
for an example configuration.
Figure 7
CCLK
FB_IN
FSEL_FB
FSELA
FSELB
FSELC
33.33 MHz (Feedback)
MPC9600 REV. 5 NOVEMBER 10, 2008
Max
Max
100
150
100
130
180
280
180
70
MPC9600
for an example.
100 MHz
100 MHz
100 MHz
25 MHz
Min
QA0–6
QB0–6
QC0–6
QFB
Typ
Typ
150
25
20
80
25
40
40
30
QC0 to QC6
QC0 to QC6
7
7
7
200 MHz
200 MHz
200 MHz
50 MHz
Max
Max
Max
130
110
250
110
133.3 MHz
66.67 MHz
66.67 MHz
50
70
70
90