ICS81006AKILFT IDT, Integrated Device Technology Inc, ICS81006AKILFT Datasheet - Page 10

• Manufacturer Part Number: ICS81006AKILFT
• Description: IC VCXO TO 6 LVCMOS OUT 20VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Voltage Controlled Crystal Oscillator (VCXO)r

Specifications of ICS81006AKILFT

• Pll: No
• Input: Crystal
• Output: LVCMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: No/No
• Frequency - Max: 31.25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 1.6 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN, 20-VFQFPN
• Frequency-max: 31.25MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 81006AKILFT

F
• C
• C
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
E
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal parameters.
For the numerical example below there were some assumptions
made. First, the stray capacitance (C
capacitance due to board parasitic, is 4pF. Second, the expected
lifetime of the project is 5 years; hence the inaccuracy due to
TPR = ±113.25ppm
APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm
The example above will ensure a total pull range of
±113.25 ppm with an APR of ±58.25ppm. Many times, board
designers may select their own cr ystal based on their
application. If the application requires a tighter APR, a crystal
IDT
T
Total
TPR
S
C
C
ABLE
ORMULAS
XAMPLE
C
C
ICS81006I
VCXO-TO-6 LVCMOS OUTPUTS
y
V
V
™
C
_
_
Low
Low
High
High
m
L
I H
C
/ ICS
O
Low
G
b
=
W
Pull
Low
H
6. V
l o
is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
determines the high frequency component on the TPR.
⎛
⎜
⎜
⎜ ⎜
⎝
is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
determines the low frequency component on the TPR.
=
2
™
=
⋅
(
VCXO-TO-LVCMOS OUTPUTS
Range
ARACTOR
C
(
P
L
H
C
220
(
C
(
0
o
0
a
g i
L
ALCULATIONS
L
+
w
1
a r
+
1
h
⋅
+
4
+
4
⎛ +
⎜
⎝
m
V
V
pf
1
C
pf
a
C
(
a
t e
TPR
a r
S
a r
S
+
1
1
9
+
r e
1
P
t c
+
15
7 .
t c
+
15
ARAMETERS
r o
r o
C
)
pF
4 .
C
4 .
=
V
C
V
pf
C
_
pf
⎛
⎜
⎜
⎜
⎜
⎝
_
4
a
Low
a
Low
2
) (
pF
p
) (
p
+
⋅
⋅
a
a
) (
C
) (
i c
0
+
⎞
⎟
⎠
i c
⋅
0
0
a t
+
−
a t
C
+
C
C
n
4
2
1
4
n
L
L
c
⋅
pf
2
S1
c
pf
⋅
2
⎛ +
⎜
⎝
e
220
e
+
1
, C
+
1
+
+
C
C
15
S2
15
C
⋅
S
S
⎛ +
⎜
⎝
), which is all the excess
2
4 .
2
Low
1
4 .
+
+
pf
pf
C
C
16
C
1
)
V
)
0
V
8 .
⎞
⎟
⎠
_
=
_
Low
Low
−
pF
9
7 .
2
)
)
4
⋅
pf
C
pF
T
0
e
C
t s
⎞
⎟
⎠
V
1
⎞
⎟
⎟
⎟ ⎟
⎠
V
⋅
C
C
⋅
⎛
⎜
⎝
C
10
1
o
=
1
=
+
n
6
3
d
0
C
3 .
= ⋅
t i
V
High
10
V
o i
226
n
C
aging is ±15ppm. Third, though many boards will not require load
tuning capacitors (C
consistent performance of the system that two tuning capacitor
pads be placed into every design. Typical values for the load tuning
capacitors will range from 0 to 4pF.
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can vary the frequency tolerance,
temperature stability, and aging or shunt capacitance to achieve
the required pullability.
s
C
5 .
0
High
⎞
⎟
⎠
ppm
⎞
⎟
⎟
⎟
⎟
⎠
⋅
=
10
C
High
(
(
6
C
C
L
L
=
1
1
+
(
+
(
0
M
0
C
C
+
+
i
S
i n
S
4
1
4
1
pf
m
+
pf
+
C
u
C
+
L1
+
m
V
V
29
, C
29
_
_
High
High
6 .
6 .
T
L2
pf
pf
ICS81006AKI REV. B OCTOBER 8, 2008
) (
y
1
2
) (
), it is recommended for long-term
+
p
⋅
9
) (
5
) (
+
c i
6 .
C
4 .
⋅
C
0
l a
L
0
L
2
+
2
+
+
+
4
4
M
C
pf
C
pf
S
a
S
2
+
2
i x
+
+
29
+
29
m
C
C
6 .
u
6 .
V
V
m
pf
_
pf
_
High
High
)
)
=
U
)
)
p
p
16
i n
F
F
s t
8 .
pf