ICS673M-01I IDT, Integrated Device Technology Inc, ICS673M-01I Datasheet - Page 4

• Manufacturer Part Number: ICS673M-01I
• Description: IC PLL BUILDING BLOCK 16-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Phase Lock Loop (PLL)r

Specifications of ICS673M-01I

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 120MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Frequency-max: 120MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 673M-01I

MDS 673-01 L
AC Electrical Characteristics
External Components
The ICS673-01 requires a minimum number of external
components for proper operation. A decoupling
capacitor of 0.01 F should be connected between VDD
and GND as close to the ICS673-01 as possible. A
series termination resistor of 33
clock output.
Special considerations must be made in choosing loop
components C
http://www.idt.com
VDD = 3.3V ±5%,
VDD = 5.0V ±10%,
Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.
Output Clock Frequency
(from pin CLK)
Input Clock Frequency
(into pins REFIN or FBIN)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
Charge Pump Current
Output Clock Frequency
(from pin CLK)
Input Clock Frequency
(into pins REFIN or FBIN)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
Charge Pump Current
S
and C
Parameter
Parameter
P
. These can be found online at
Ambient Temperature -40 to +85 C, C
Ambient Temperature -40 to +85 C, C
may be used at the
Symbol
Symbol
f
f
f
f
t
t
t
t
REF
t
REF
t
CLK
K
CLK
K
I
I
OR
OF
DC
OR
OF
DC
t
cp
t
cp
J
J
O
O
w w w. i d t . c o m
4
SEL = 1
SEL = 0
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
SEL = 1
SEL = 0
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
Avoiding PLL Lockup
In some applications, the ICS673-01 can “lock up” at
the maximum VCO frequency. This is usually caused
by power supply glitches or a very slow power supply
ramp. This situation also occurs if the external divider
starts to fail at high input frequencies. The usual failure
mode of a divider circuit is that the output of the divider
begins to miss clock edges. The phase detector
interprets this as a too low output frequency and
Conditions
Conditions
LOAD
LOAD
at CLK = 15 pF, unless stated otherwise
at CLK = 15 pF,
Note 1
Note 1
Min.
Min.
0.25
0.25
40
45
1
1
PLL B
Typ. Max. Units
Typ. Max. Units
0.75
250
190
150
190
1.2
2.5
0.5
0.5
2.4
50
50
unless stated otherwise
UILDING
Revision 051310
100
120
1.5
25
60
30
55
8
2
8
1
1
ICS673-01
B
MHz/V
MHz/V
MHz
MHz
MHz
MHz
MHz
MHz
LOCK
ns
ns
ps
ns
ns
ps
%
%
A
A