ICS673M-01I IDT, Integrated Device Technology Inc, ICS673M-01I Datasheet - Page 7

• Manufacturer Part Number: ICS673M-01I
• Description: IC PLL BUILDING BLOCK 16-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Phase Lock Loop (PLL)r

Specifications of ICS673M-01I

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 120MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Frequency-max: 120MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 673M-01I

MDS 673-01 L
Determining the Loop Filter Values
The loop filter components consist of C
Calculating these values is best illustrated by an
example. Using the example in Figure 1, we can
synthesize 20 MHz from a 200 kHz input.
The phase locked loop may be approximately
described by the following equations:
As a general rule, the bandwidth should be at least 20
times less than the reference frequency, i.e.,
In this example, using the above equation, bandwidth
should be less than or equal to 10 kHz. By setting the
bandwith to 10kHz and using the first equation, R
be determined since all other variables are known. In
the example of Figure 1, N = 200, comprising the divide
by 2 on the chip (VCO post divider) and the external
divide by 100. Therefore, the bandwidth equation
becomes:
and R
0,000
Bandwidth
Damping factor,
where:
BW REFIN
S
= 26 k
K
I
N = Total feedback divide from VCO,
C
R
cp
O
S
S
=
= Charge pump current (A)
= VCO gain (Hz/V)
= Loop filter capacitor (Farads)
= Loop filter resistor (Ohms)
including the internal VCO post divider
R
--------------------------------------------------------------------
NBW
S
190
=
20
=
R
----- -
R
------------------------------- -
2
2
S
S
10
K
---------------------------------- -
2 N
6
K
200
O
O
2.5
I
I
CP
N
CP
S
, C
10
P
C
, and R
–
S
S
w w w. i d t . c o m
can
S
7
.
0.7
Choosing a damping factor of 0.7 (a minimal damping
factor than can be used to ensure fast lock time),
damping factor equation becomes:
and C
value).
The capacitor C
charge pump and should be approximately 1/20th the
size of C
Therefore, C
To summarize, the loop filter components are:
When choosing either CLK1 or CLK2 to drive the
feedback divider, IDT recommends that CLK2 be used
so that the rising edges of CLK1, CLK2, and REFIN are
all synchronized. If CLK1 is used to feedback, CLK2
may be either a rising or falling edge when compared to
CLK1 and REFIN.
=
C
C
C
R
S
25 000
--------------- -
P
S
P
S
= 1.32 nF (1.2 nF is the nearest standard
,
S
2
= 1.2 nf
= 56 pf
= 26 k
, i.e.,
C
P
S
= 60 pF (56 pF nearest standard value).
190
--------------------------------------------------------------------------
P
20
is used to damp transients from the
10
6
PLL B
200
2.5
UILDING
10
Revision 051310
–
ICS673-01
6
B
C
LOCK
S