MPC9772AE IDT, Integrated Device Technology Inc, MPC9772AE Datasheet - Page 8

• Manufacturer Part Number: MPC9772AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9772AE

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:18
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772 Configurations
the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
where f
clock source (CCLKO, CCLK1 or XTAL interface), M is the
PLL feedback divider and N is a output divider. The PLL
feedback divider is configured by the FSEL_FB[2:0] and the
output dividers are individually configured for each output
bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0]
inputs.
feedback-divider M is limited by the specified VCO frequency
range. f
frequency range of 200 to 480 MHz in order to achieve stable
PLL operation:
or a divide-by-two and can be used to situate the VCO into
Configuring the MPC9772 amounts to properly configuring
The reference frequency f
The PLL post-divider VCO_SEL is either a divide-by-one
f
REF
REF
REF
f
VCO,MIN
is the reference frequency of the selected input
and M must be configured to match the VCO
≤
PLL
÷M
(f
REF
f
OUT
⋅
VCO_SEL
= f
÷VCO_SEL
REF
REF
⋅ M ÷ N
and the selection of the
⋅
M)
≤
f
÷N
VCO,MAX
APPLICATIONS INFORMATION
f
OUT
8
the specified frequency range. This divider is controlled by
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio.
the VCO frequency and output divider:
Table 11. MPC9772 Divider
dividers and
configurations for the MPC9772:
Divider
The output frequency for each bank can be derived from
Table 11
N
N
N
M
f
f
f
A
B
C
QA[0:3]
QB[0:3]
QC[0:3]
Bank C Output
Bank A Output
Bank B Output
FSEL_FB[0:3]
PLL feedback
shows the various PLL feedback and output
= f
= f
= f
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
Figure 3
Function
Divider
Divider
Divider
VCO
VCO
VCO
÷ (VCO_SEL ⋅ N
÷ (VCO_SEL ⋅ N
÷ (VCO_SEL ⋅ N
and
Figure 4
VCO_SEL
MPC9772 REV 6 FEBRUARY 7, 2007
÷1
÷2
÷1
÷2
÷1
÷2
÷1
÷2
display example
A
B
C
)
)
)
8, 12, 16, 20, 24, 32, 40
4, 6, 8, 10, 12, 16
8, 12, 16, 24
8, 12, 16, 20
4, 8, 12, 16
4, 6, 8, 12
4, 6, 8, 10
2, 4, 6, 8
Values