MPC9772AE IDT, Integrated Device Technology Inc, MPC9772AE Datasheet - Page 9

• Manufacturer Part Number: MPC9772AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9772AE

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:18
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772 Individual Output Disable
(Clock Stop) Circuitry
MPC9772 allows designers, under software control, to
implement power management into the clock distribution
design. A simple serial interface and a clock stop control logic
provides a mechanism through which the MPC9772 clock
outputs can be individually stopped in the logic ‘0’ state: The
clock stop mechanism allows serial loading of a 12-bit serial
input register. This register contains one programmable clock
stop bit for 12 of the 14 output clocks. The QC0 and QFB
outputs cannot be stopped (disabled) with the serial port.
writing logic ‘0’ to the respective stop enable bit. Likewise, the
SYNC Output Description
QSYNC. In configurations with the output frequency
relationships are not integer multiples of each other QSYNC
provides a signal for system synchronization purposes. The
MPC9772 monitors the relationship between the A bank and
the B bank of outputs. The QSYNC output is asserted (logic
low) one period in duration and one period prior to the
MPC9772 example configuration (feedback of QFB = 33.3 MHz,
f
f
VCO
ref
The individual clock stop (output enable) control of the
The user can program an output clock to stop (disable) by
The MPC9772 has a system synchronization pulse output
Frequency Range
= 33.3 MHz
=400 MHz, VCO_SEL=÷1, M=12, N
QC Outputs
QA Outputs
QA Outputs
Input
Figure 3. Example Configuration
STOP_DATA
101
11
00
00
STOP_CLK
1
FSEL_FB[2:0]
CCLK0
CCLK1
CCLK_SEL
VCO_SEL
FB_IN
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
33.3 MHz (Feedback)
T
MPC9772
A
100 – 240 MHz
16.6 – 40 MHz
16.6 – 40 MHz
50 – 120 MHz
= 0°C to +70°C
START
QC[3:0]
QA[3:0]
QB[3:0]
QFB
QA0
Figure 5. Clock Stop Circuit Programming
A
QA1
=12, N
T
A
16.6 – 38.33 MHz
16.6 – 38.33 MHz
100 – 230 MHz
= –40°C to +85°C
50 – 115 MHz
QA2
33.3 MHz
100 MHz
200 MHz
B
=4, N
QA3
C
=2).
QB0
9
MPC9772 example configuration (feedback of QFB = 25 MHz,
f
user may programmably enable an output clock by writing
logic ‘1’ to the respective enable bit. The clock stop logic
enables or disables clock outputs during the time when the
output would be in normally in logic low state, eliminating the
possibility of short or ‘runt’ clock pulses.
STOP_DATA input by supplying a logic ‘0’ start bit followed
serially by 12 NRZ disable/enable bits. The period of each
STOP_DATA bit equals the period of the free—running
STOP_CLK signal. The STOP_DATA serial transmission
should be timed so the MPC9772 can sample each
STOP_DATA bit with the rising edge of the free—running
STOP_CLK signal. (See
coincident rising edges of the QA and QC outputs. The
duration and the placement of the pulse is dependent QA and
QC output frequencies: the QSYNC pulse width is equal to
the period of the higher of the QA and QC output frequencies.
Figure 6
The QSYNC output is defined for all possible combinations of
the bank A and bank C outputs.
VCO
QB1
Frequency Range
The user can write to the serial input register through the
f
ref
=250 MHz, VCO_SEL=÷1, M=10, N
QA Outputs
QA Outputs
QC Outputs
= 25 MHz
QB2
Input
shows various waveforms for the QSYNC output.
011
Figure 4. Example Configuration
QB3
00
00
00
1
FSEL_FB[2:0]
CCLK0
CCLK1
CCLK_SEL
VCO_SEL
FB_IN
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
25 MHz (Feedback)
T
QC1
A
100 – 240 MHz
50 – 120 MHz
50 – 120 MHz
MPC9772
20 – 48 MHz
= 0°C to +70°C T
Figure
MPC9772 REV 6 FEBRUARY 7, 2007
QC2
QC[3:0]
5.)
QA[3:0]
QB[3:0]
QFB
QC3
A
=4, N
A
QSYNC
100 – 230 MHz
= –40°C to +85°C
50 – 115 MHz
50 – 115 MHz
20 – 46 MHz
B
=4, N
62.5 MHz
62.5 MHz
125 MHz
C
=2).