IDT74FCT388915TDJG8 IDT, Integrated Device Technology Inc, IDT74FCT388915TDJG8 Datasheet

IC PLL CLK GENERATOR 3ST 28-PLCC

IDT74FCT388915TDJG8

Manufacturer Part Number
IDT74FCT388915TDJG8
Description
IC PLL CLK GENERATOR 3ST 28-PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
74FCTr
Type
PLL Clock Driverr
Datasheet

Specifications of IDT74FCT388915TDJG8

Pll
Yes with Bypass
Input
LVTTL
Output
LVCMOS, LVTTL
Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
No/No
Frequency - Max
133MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Frequency-max
133MHz
Number Of Elements
1
Pll Input Freq (min)
10MHz
Pll Input Freq (max)
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
PLCC
Output Frequency Range
10 to 133MHz
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Pin Count
28
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74FCT388915TDJG8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT74FCT388915TDJG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
© 2004 Integrated Device Technology, Inc.
FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x output,
• 3-State outputs
• Duty cycle distortion < 500ps (max.)
• 32/–16mA drive at CMOS output voltage levels
• V
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC and SSOP packages
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
FUNCTIONAL BLOCK DIAGRAM
COMMERCIAL TEMPERATURE RANGE
(FREQ_SEL = HIGH)
one ÷2 output; all outputs are TTL-compatible
CC
= 3.3V ± 0.3V
FEED BAC K
FREQ_SEL
REF_SEL
SYNC (0)
SYNC (1)
PLL_EN
OE/RST
0
1
M
u
x
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
Phase/Freq.
Detector
0
Divide
-By-2
M ux
1
(
(
÷
÷
1)
2)
1
DESCRIPTION:
quency and phase of outputs to the input reference clock. It provides low
skew clock distribution for high performance PCs and workstations. One of
the outputs is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of the phase/
frequency detector, charge pump, loop filter and VCO. The VCO is
designed for a 2Q operating frequency range of 40MHz to f2Q Max.
Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at half the
Q frequency.
path. PLL _EN allows bypassing of the PLL, which is useful in static test
modes. When PLL_EN is low, SYNC input may be used as a test clock. In
this test mode, the input frequency is not limited to the specified range and
the polarity of outputs is complementary to that in normal operation (PLL_EN
= 1). The LOCK output attains logic HIGH when the PLL is in steady-state
phase and frequency lock. When OE/RST is low, all the outputs are put in
high impedance state and registers at Q, Q and Q/2 outputs are reset.
recommended in Figure 3.
The FCT388915T uses phase-lock loop technology to lock the fre-
The FCT388915T provides 8 outputs, the Q5 output is inverted from the
The FREQ_SEL control provides an additional ÷ 2 option in the output
The FCT388915T requires one external loop filter component as
Charge Pum p
1
0
M
u
x
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
R
R
R
R
R
R
R
COMMERCIAL TEMPERATURE RANGE
Q
Q
Q
Q
Q
Q
Q
Q
Controlled
Oscilator
Voltage
IDT74FCT388915T
70/100/133/150
OCTOBER 2008
LOCK
LF
2Q
Q0
Q1
Q2
Q3
Q4
Q5
Q/2
DSC-4243/7

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IDT74FCT388915TDJG8 Summary of contents

Page 1

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH) • Max. output frequency: 150MHz • Pin and function compatible with FCT88915T, MC88915T ...

Page 2

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) PIN CONFIGURATION 1 GND OE/RST 5 FEEDBACK 6 REF_SEL 7 SYNC( (AN GND(AN) 10 SYNC( FREQ_SEL GND 13 ...

Page 3

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) ABSOLUTE MAXIMUM RATINGS Symbol Description V (2) Terminal Voltage with Respect to GND TERM (3) V Terminal Voltage with Respect to GND TERM (4) V Terminal Voltage with Respect to GND ...

Page 4

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) POWER SUPPLY CHARACTERISTICS Symbol Parameter ΔI Quiescent Power Supply Current CC TTL Inputs HIGH (4) I Dynamic Power Supply Current CCD C Power Dissipation Capacitance PD (6) I Total Power Supply ...

Page 5

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter t Rise/Fall Time RISE/FALL All Outputs (between 0.8V and 2V) PULSE WIDTH (3) t Output Pulse Width Q, Q, Q/2 outputs (3) Q0-Q4, Q5, ...

Page 6

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) GENERAL AC SPECIFICATION NOTES (continued): 8. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature and ...

Page 7

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q/2 output is ...

Page 8

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) CLOCK @ f SYSTEM CLO DISTRIBUTE CLO CLOCK @ 2f at point of use Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication ...

Page 9

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) TEST CIRCUITS AND WAVEFORMS Pulse D.U.T. Generator Ω Ω Ω Ω Ω / SYNC IN ...

Page 10

IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) ORDERING INFORMATION XX XXXX FCT Temp. Range Device Type NOTE: 1. When ordering GREEN packages, replace this numeric value with the equivalent letter below MHz (JG or PYG) C= ...

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