STW81101AT STMicroelectronics, STW81101AT Datasheet - Page 21

• Manufacturer Part Number: STW81101AT
• Description: IC SYNTHESIZER MULTI RF 28VFQFPN
• Manufacturer: STMicroelectronics
• Type: Frequency Synthesizer (RF)r

Specifications of STW81101AT

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: No/No
• Frequency - Max: 4.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 4.4GHz
• Number Of Elements: 1
• Pll Input Freq (min): 10MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STW81101
5.5
5.6
5.7
Phase frequency detector (PFD)
The PFD takes inputs from the reference and the VCO dividers and produces an output
proportional to the phase error. The PFD includes a delay gate that controls the width of the
anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer
function.
Figure 17
Figure 17. PFD diagram
Lock detect
This signal indicates that the difference between rising edges of both UP and DOWN PFD
signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is
high when the PLL is locked and low when the PLL is unlocked. Lock Detect consumes
current only during PLL transients.
Charge pump
This block drives two matched current sources, I
respectively by UP and DOWN PFD outputs. The nominal value of the output current is
controlled by an external resistor (to be connected to the REXT input pin) and a 3-bit word
that allows selection among 8 different values.
The minimum value of the output current is: I
is a simplified schematic of the PFD.
VDD
VDD
F ref
F
ref
D FF
D FF
R
R
MIN
Delay
UP
= 2*VBG/REXT (VBG~1.17 V)
ABL
and I
DOWN
, which are controlled
Down
Up
Circuit description
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