STW81101AT STMicroelectronics, STW81101AT Datasheet - Page 27

• Manufacturer Part Number: STW81101AT
• Description: IC SYNTHESIZER MULTI RF 28VFQFPN
• Manufacturer: STMicroelectronics
• Type: Frequency Synthesizer (RF)r

Specifications of STW81101AT

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: No/No
• Frequency - Max: 4.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 4.4GHz
• Number Of Elements: 1
• Pll Input Freq (min): 10MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STW81101
6
6.1
6.1.1
6.1.2
I
The I
Data is transmitted from microprocessor to the STW81101 through the 2-wire (SDA and
SCL) I
The I
any device that reads the data as a receiver. The device controlling the data transfer is the
master, and the others are slaves. The master always initiates the transfer and provides the
serial clock for synchronization.
General features
Data validity
Data changes on the SDA line must only occur when the SCL is low. SDA transitions while
the clock is high are used to identify a START or STOP condition.
Figure 20. Data validity
START and STOP conditions
START condition
A START condition is identified by a transition of the data bus SDA from high to low while the
clock signal SCL is stable in the high state. A START condition must precede any data
transfer command.
STOP condition
A STOP condition is identified by a transition of the data bus SDA from low to high while the
clock signal SCL is stable in the high state. A STOP condition terminates communications
between the STW81101 and the bus master.
2
SDA
SCL
C bus interface
2
2
C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 0 V.
C bus protocol defines any device that sends data on the bus as a transmitter, and
2
C bus interface. The STW81101 is always a slave device.
Data line
Stable data
Valid
Change
allowed
data
I
2
C bus interface
PC00406
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