IDT82V3280DQG8 IDT, Integrated Device Technology Inc, IDT82V3280DQG8 Datasheet - Page 135
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IDT82V3280DQG8
Manufacturer Part Number
IDT82V3280DQG8
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of IDT82V3280DQG8
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280DQG8
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T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration
Programming Information
IDT82V3280
Address: 6AH
Type: Read / Write
Default Value: XX01XX01
7 - 6
5 - 4
3 - 2
1 - 0
Bit
7
-
T0_APLL_BW[1:0]
T4_APLL_BW[1:0]
Name
-
-
6
-
Reserved.
These bits set the bandwidth for T0 APLL.
00: 100 kHz.
01: 500 kHz. (default)
10: 1 MHz.
11: 2 MHz.
Reserved.
These bits set the bandwidth for T4 APLL.
00: 100 kHz.
01: 500 kHz. (default)
10: 1 MHz.
11: 2 MHz.
T0_APLL_BW1
5
T0_APLL_BW0
4
135
3
-
Description
2
-
T4_APLL_BW1
1
December 9, 2008
T4_APLL_BW0
0
WAN PLL
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