IDT82V3280DQG8 IDT, Integrated Device Technology Inc, IDT82V3280DQG8 Datasheet - Page 141
IDT82V3280DQG8
Manufacturer Part Number
IDT82V3280DQG8
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of IDT82V3280DQG8
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280DQG8
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OUT6_FREQ_CNFG - Output Clock 6 Frequency Configuration
Programming Information
IDT82V3280
Address:70H
Type: Read / Write
Default Value: 00000110
OUT6_PATH_S
7 - 4
3 - 0
Bit
EL3
7
OUT6_PATH_SEL[3:0]
OUT6_DIVIDER[3:0]
OUT6_PATH_S
Name
EL2
6
These bits select an input to OUT6.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT6.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
(selected by the OUT6_PATH_SEL[3:0] bits (b7~4, 70H)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to
Table 25
OUT6_PATH_S
EL1
5
for the division factor selection.
Table 24
OUT6_PATH_S
for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
EL0
4
141
OUT6_DIVIDER
3
3
Description
OUT6_DIVIDER
2
2
OUT6_DIVIDER
1
1
December 9, 2008
OUT6_DIVIDER
0
0
WAN PLL
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