IDT82V3280DQG IDT, Integrated Device Technology Inc, IDT82V3280DQG Datasheet - Page 43
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IDT82V3280DQG
Manufacturer Part Number
IDT82V3280DQG
Description
IC PLL WAN SE STRATUM 2 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Specifications of IDT82V3280DQG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP EP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3280DQG
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Table 28: Related Bit / Register in Chapter 3.13
Functional Description
IDT82V3280
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing
output signals
Output clocks
T0 selected
EX_SYNC1
Frame sync
input clock
OUTn_PATH_SEL[3:0] (1 ≤ n ≤ 7)
OUTn_DIVIDER[3:0] (1 ≤ n ≤ 7)
OUTn_INV (1 ≤ n ≤ 7 or n = 9)
EX_SYNC_ALARM_MON
2K_8K_PUL_POSITION
AUTO_EXT_SYNC_EN
SYNC_MON_LIMT[2:0]
EX_SYNC_ALARM
EX_SYNC_ALARM
OUT6_PECL_LVDS
OUT7_PECL_LVDS
OUT8_PATH_SEL
OUT9_PATH_SEL
T4_INPUT_FAIL
T4_INPUT_FAIL
SYNC_PH1[1:0]
AMI_OUT_DUTY
IN_SONET_SDH
EXT_SYNC_EN
400HZ_SEL
OUT8_EN
OUT9_EN
8K_PUL
2K_PUL
8K_INV
2K_INV
8K_EN
2K_EN
Bit
1
2
1
2
43
OUT1_FREQ_CNFG ~ OUT7_FREQ_CNFG
OUT9_FREQ_CNFG, OUT8_FREQ_CNFG
DIFFERENTIAL_IN_OUT_OSCI_CNFG
Figure 12. 1 UI Late Frame Sync Input Signal Timing
INTERRUPTS3_ENABLE_CNFG
output signals
Output clocks
EX_SYNC1
Frame sync
T0 selected
input clock
SYNC_MONITOR_CNFG
FR_MFR_SYNC_CNFG
SYNC_PHASE_CNFG
INPUT_MODE_CNFG
INTERRUPTS3_STS
OUT8_FREQ_CNFG
OUT9_FREQ_CNFG
OPERATING_STS
Register
December 9, 2008
Address (Hex)
6B ~ 71
73, 72
0A
7C
7D
72
73
09
74
52
0F
12
WAN PLL
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