IDT82V3280DQG IDT, Integrated Device Technology Inc, IDT82V3280DQG Datasheet - Page 53

• Manufacturer Part Number: IDT82V3280DQG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280DQG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP EP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280DQG

Table 36: Write Timing Characteristics in Intel Mode
Microprocessor Interface
IDT82V3280
Symbol
t
t
t
t
t
t
t
t
t
pw1
pw2
t
t
t
t
t
su1
su2
su3
t
out
T
d2
d5
d6
h1
h2
h3
h4
TI
in
( WR rising edge to WR falling edge, or WR rising edge to RD falling edge)
AD[7:0]
A[6:0]
Time between consecutive Write-Read or Write-Write accesses
WR
CS
RDY
RD
Valid address after WR rising edge hold time
Valid data before WR rising edge setup time
CS rising edge to RDY release delay time
Valid WR after RDY rising edge hold time
Valid data after WR rising edge hold time
Valid CS after WR rising edge hold time
WR rising edge to RDY low delay time
Valid address to valid CS setup time
One cycle time of the master clock
Valid CS to valid RDY delay time
Valid CS to valid WR setup time
Valid RDY pulse width low
Valid WR pulse width low
t
Delay of output pad
High-Z
su1
Delay of input pad
Parameter
Figure 20. Intel Write Timing Diagram
t
d2
t
su2
address
53
t
pw2
t
pw1
t
su3
data
t
h3
1.5T + 10
1.5T + 10
Min
>7T
0
0
3
0
0
0
9
t
t
h1
h4
t
h2
t
d5
12.86
Typ
13
13
13
5
5
t
d6
High-Z
Max
December 9, 2008
WAN PLL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns