SI4122-D-GT Silicon Laboratories Inc, SI4122-D-GT Datasheet - Page 23
![IC SYNTHESIZER RF2/IF 24TSSOP](/photos/6/54/65473/336-24-tssop_sml.jpg)
SI4122-D-GT
Manufacturer Part Number
SI4122-D-GT
Description
IC SYNTHESIZER RF2/IF 24TSSOP
Manufacturer
Silicon Laboratories Inc
Type
Frequency Synthesizerr
Datasheet
1.SI4112-D-GT.pdf
(36 pages)
Specifications of SI4122-D-GT
Number Of Circuits
1
Package / Case
24-TSSOP
Pll
Yes
Input
Clock
Output
Clock
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
1.5GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
1.5GHz
Maximum Input Frequency
62.5 MHz to 1000 MHz
Minimum Input Frequency
2 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.7 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1173
Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001
*Note: When AUTOK
Name
Bit
17:6
Bit
5:4
3:2
1:0
for programming Phase Detector Gain.
D17 D16 D15 D14 D13 D12 D11 D10 D9
0
0
P
Reserved
= 1, these bits do not need to be programmed. When AUTOK
K
K
0
K
Name
P2
P1
PI
[1:0]
[1:0]
[1:0]
0
0
0
Program to zero.
IF Phase Detector Gain Constant.*
N Value
<2048
2048–4095
4096–8191
>8191
RF2 Phase Detector Gain Constant.*
N Value
<4096
4096–8191
8192–16383
>16383
RF1 Phase Detector Gain Constant.*
N Value
<8192
8192–16383
16384–32767
>32767
0
0
Rev. 1.61
= 00
= 01
= 10
= 00
= 01
= 10
= 11
= 00
= 01
= 11
K
= 11
K
K
= 10
0
PI
P2
P1
D8
0
D7
0
Function
D6
0
P
= 0, use these recommended values
D5
K
PI
[1:0]
D4
D3
K
P2
[1:0]
D2
Si4133
D1
K
P1
[1:0]
D0
23