SI5322-C-GM Silicon Laboratories Inc, SI5322-C-GM Datasheet - Page 10

• Manufacturer Part Number: SI5322-C-GM
• Description: IC PREC CLOCK MULTIPLIER 36-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5322-C-GM

• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.05GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Frequency-max: 1GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5322
10
GND PAD
7, 18, 36
Pin #
33
30
34
35
29
28
CKOUT2–
CKOUT2+
CKOUT1–
CKOUT1+
Pin Name
SFOUT0
SFOUT1
GND
NC
Table 3. Si5322 Pin Descriptions (Continued)
GND
I/O
—
O
O
I
Signal Level
3-Level
Supply
Multi
Multi
—
Preliminary Rev. 0.5
Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2. Valid settings include LVPECL, LVDS, and
CML. Also includes selections for CMOS mode, tristate
mode, and tristate/sleep mode.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
No Connect.
These pins must be left unconnected for normal operation.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
SFOUT[1:0]
MM
HM
MH
HH
ML
LM
HL
LH
LL
Description
Reserved
LVDS
CML
LVPECL
Reserved
LVDS—Low Swing
CMOS
Disabled
Reserved
Signal Format