SI5368A-B-GQ Silicon Laboratories Inc, SI5368A-B-GQ Datasheet - Page 12
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SI5368A-B-GQ
Manufacturer Part Number
SI5368A-B-GQ
Description
IC ANY-RATE MULTI/ATTEN 100TQFP
Manufacturer
Silicon Laboratories Inc
Type
Clock Multiplierr
Specifications of SI5368A-B-GQ
Number Of Circuits
1
Package / Case
100-TQFP, 100-VQFP
Pll
Yes with Bypass
Input
Clock
Output
CML, CMOS, LVDS, LVPECL
Ratio - Input:output
4:5
Differential - Input:output
Yes/Yes
Frequency - Max
1.4GHz
Divider/multiplier
No/Yes
Voltage - Supply
1.62 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
1.4GHz
Maximum Input Frequency
710 MHz
Minimum Input Frequency
0.002 MHz
Output Frequency Range
0.002 MHz to 1417 MHz
Supply Voltage (max)
2.75 V
Supply Voltage (min)
1.62 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V, 2.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI5368A-B-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Si5368
12
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
GND PAD
Pin #
71
77
78
82
83
87
88
90
92
93
97
98
CKOUT3+
CKOUT3–
CKOUT1–
CKOUT1+
CKOUT2+
CKOUT2–
CKOUT4–
CKOUT4+
Pin Name
FS_OUT–
FS_OUT+
GND PAD
CMODE
SDI
GND
I/O
Table 3. Si5368 Pin Descriptions (Continued)
O
O
O
O
O
I
I
Signal Level
LVCMOS
LVCMOS
Supply
MULTI
MULTI
MULTI
MULTI
MULTI
Preliminary Rev. 0.3
Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the serial data input.
In I
ignored.
This pin has a weak pull-down.
Clock Output 3.
Differential clock output. Output signal format is selected by
SFOUT3_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Clock Output 1.
Differential clock output. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Frame Sync Output.
Differential frame sync output or fifth high-speed clock output.
Output signal format is selected by SFOUT_FSYNC_REG reg-
ister bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs. Duty cycle and active
polarity are controlled by FSYNC_PW and FSYNC_POL bits,
respectively. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock Fam-
ily Reference Manual.
Control Mode.
Selects I
0 = I
1 = SPI Control Mode.
Clock Output 2.
Differential clock output. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Clock Output 4.
Differential clock output. Output signal format is selected by
SFOUT4_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
2
C microprocessor control mode (CMODE = 0), this pin is
2
C Control Mode.
2
C or SPI control mode for the device.
Description