CY28346ZXCT Cypress Semiconductor Corp, CY28346ZXCT Datasheet - Page 15

• Manufacturer Part Number: CY28346ZXCT
• Description: IC CLOCK SYNTHESIZER 56-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Synchronizer, Fanout Distribution, Spread Spectrum Clock Generatorr

Specifications of CY28346ZXCT

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 5:17
• Differential - Input:output: No/Yes
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP II
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07331 Rev. *C
AC Parameters
T
T
DeltaT
DeltaT
V
CPU at 1.0V Timing
T
T
T
T
Differential
T
SE–
DeltaSlew
V
3V66
T
T
T
T
T
T
Unbuffered
T
Buffered
T
Notes:
20. Measurement taken from differential waveform, from –0.35V to +0.35V.
21. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the instantaneous difference
22. Measured in absolute voltage, i.e., single-ended measurement.
23. THIGH is measured at 2.4V for non-host outputs.
24. TLOW is measured at 0.4V for all outputs.
25. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data
CCJ
R
DC
PERIOD
SKEW
CCJ
R
DC
PERIOD
HIGH
LOW
R
SKEW
SKEW
CCJ
CROSS
CROSS
Parameter
/T
/T
/T
between maximum CLK rise (fall) and minimum CLK# fall (rise) time or minimum CLK rise (fall) and maximum CLK# fall (rise) time.” This parameter is designed
form waveform symmetry.
sheet).
F
F
F
R
F
CPU Cycle to Cycle
Jitter
CPUT and CPUC Rise
and Fall Times
Rise/Fall Matching
Rise Time Variation
Fall Time Variation
Crossing Point Voltage
at 0.7V Swing
CPUT and CPUC Duty
Cycle
CPUT and CPUC
Period
Any CPU to Any CPU
Clock Skew
CPU Cycle to Cycle
Jitter
CPUT and CPUC Rise
and Fall Times
Absolute Single- ended
Rise/Fall Waveform
Symmetry
Cross Point at 1.0V
swing
3V66 Duty Cycle
3V66 Period
3V66 HIGH Time
3V66 LOW Time
3V66 Rise and Fall
Times
3V66 to 3V66 Clock
Skew
3V66 to 3V66 Clock
Skew
DRCG Cycle to Cycle
Jitter
(V
DD
Description
= V
DDA
= 3.3V ±5%, T
14.85
Min.
15.0
4.95
4.55
175
280
175
510
0.5
45
45
66 MHz
A
= 0°C to +70°C) (continued)
Max.
20%
15.3
15.3
150
700
125
125
430
100
150
467
325
760
500
250
250
2.0
55
55
Min.
9.85
15.0
4.95
4.55
175
280
175
510
0.5
45
45
100 MHz
Max.
20%
10.2
15.3
150
700
125
125
430
100
150
467
325
760
500
250
250
2.0
55
55
Min.
7.35
15.0
4.95
4.55
175
280
175
510
0.5
45
45
133 MHz
Max.
20%
7.65
15.3
150
700
125
125
430
100
150
467
325
760
500
250
250
2.0
55
55
Min.
4.85
15.0
4.95
4.55
175
280
175
510
0.5
45
45
200 MHz
Max.
20%
15.3
760
150
700
125
125
430
100
150
467
325
500
250
250
5.1
2.0
55
55
CY28346
Unit
Page 15 of 20
mV
mV
nS
pS
pS
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ps
ps
ps
%
%
9, 12, 13
15, 16,
15, 17,
17, 18,
12, 15,
Notes
17, 19
17, 19
15, 19
15, 16
15, 16
12, 16
15, 20
21, 22
12, 13
12, 13
12, 13
12, 13
19
20
19
16
22
23
24
25