CY2213ZXC-2T Cypress Semiconductor Corp, CY2213ZXC-2T Datasheet - Page 5

• Manufacturer Part Number: CY2213ZXC-2T
• Description: IC PROG PECL CLOCK GEN 16-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY2213ZXC-2T

• Number Of Circuits: 1
• Package / Case: 16-TSSOP
• Pll: Yes
• Input: Crystal
• Output: LVPECL
• Ratio - Input:output: 1:2
• Differential - Input:output: No/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 500MHz
• Maximum Input Frequency: 133 MHz
• Minimum Input Frequency: 1 MHz
• Output Frequency Range: 125 MHz to 500 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07263 Rev. *E
State Transition Characteristics
Specifies the maximum settling time of the CLK and CLKB
outputs from device power-up. For V
sequences are allowed to power-up and power-down the
CY2213.
AC Device Characteristics
V
t
t
t
t
t
t
t
t
Phase Noise
DC
t
t
BW
CYCLE
JCRMS
JCPK
JPRMS
JPPK
JLT
JLT
JLT
DC,ERR
CR
DD
, t
Parameter
LOOP
/V
From
CF
DDX
On CLK/CLKB Normal
Clock cycle time
Cycle-to-cycle RMS jitter
At 125-MHz frequency
At 400-/500-MHz frequency
Cycle-to-cycle jitter (pk-pk)
At 125-MHz frequency
At 200-MHz frequency, XF = 25 MHz
At 400-/500-MHz frequency
Period jitter RMS
At 125-MHz frequency
At 400-/500-MHz frequency
Period jitter (pk-pk)
At 125-MHz frequency
At 200-MHz frequency, XF = 25 MHz
At 400-/500-MHz frequency
Long term RMS Jitter (P < 20)
At 125-MHz frequency
At 400-/500-MHz frequency
Long term RMS Jitter (20 < P < 40)
At 125-MHz frequency
At 400-/500-MHz frequency
Long-term RMS Jitter (40 < P < 60)
At 125-MHz frequency
At 400-/500-MHz frequency
Phase Noise at 10 kHz (x8 mode) @ 125 MHz
Long-term average output duty cycle
Cycle-cycle duty cycle error at x8 with
15.625-MHz input
Output rise and fall times (measured at 20% –
80% of V
PLL Loop Bandwidth
To
OHmin
and V
Transition Latency
Description
OLmax
DD
3 ms
and V
)
DDX
Time from V
any
DD
2.50 (400 MHz)
50 kHz (–3 dB)
/V
DDX
–107
Min.
100
45
is applied and settled to CLK/CLKB outputs settled.
Description
8 MHz (–20 dB)
8.00 (125 MHz)
43.75/35
43.75/35
62.5/50
87.5/70
0.25%
1.75%
0.25%
1.75%
6.25/5
6.25/5
50/40
Max.
2.0%
2.5%
3.5%
140
160
140
200
280
–92
400
20
55
20
65
55
70
CY2213
% t
% t
% t
% t
Page 5 of 10
% t
% t
% t
Unit
dBc
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
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