LMX2315TM National Semiconductor, LMX2315TM Datasheet - Page 18

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LMX2315TM

Manufacturer Part Number
LMX2315TM
Description
IC FREQ SYNTHESIZER 20-TSSOP
Manufacturer
National Semiconductor
Series
PLLatinum™r
Type
PLL Frequency Synthesizerr
Datasheet

Specifications of LMX2315TM

Pll
Yes
Input
CMOS, TTL
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
1.2GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
1.2GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*LMX2315TM

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Application Information
MEASUREMENT RESULTS (Example # 1)
The reference spurious level is
filter attenuation and the low spurious noise level of the
LMX2315.
The phase noise level at 10 kHz offset is −80 dBc/Hz.
FIGURE 6. PLL Phase Noise 10 kHz Offset
FIGURE 5. PLL Reference Spurs
<
−74 dBc, due to the loop
(Continued)
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18
The phase noise level at 1 kHz offset is −79.5 dBc/Hz.
Of concern in any PLL loop filter design is the time it takes to
lock in to a new frequency when switching channels. Figure
8 shows the switching waveforms for a frequency jump of
865 MHz to 915 MHz. By narrowing the frequency span of
the HP53310A Modulation Domain Analyzer enables evalu-
ation of the frequency lock time to within
time is seen to be less than 500 µs for a frequency jump of
50 MHz.
Example # 2
K
K = 2.8 mA (*)
RF
F
N = RF
ATTEN = 12 dB
p
ref
VCO
p
opt
= 43
= 2
= 300 kHz
= 34 MHz/V
= 1665 MHz
FIGURE 7. PLL Phase Noise
opt
*
FIGURE 8. Frequency Jump Lock Time
/f
20 kHz = 1.256e5
ref
= 5550
@
1 kHz Offset
±
500 Hz. The lock
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