MC12429FNR2 Freescale Semiconductor, MC12429FNR2 Datasheet - Page 2

• Manufacturer Part Number: MC12429FNR2
• Description: IC CLOCK SYNTHESIZER 28-PLCC
• Manufacturer: Freescale Semiconductor
• Type: Clock/Frequency Synthesizerr

Specifications of MC12429FNR2

• Pll: Yes
• Input: Crystal
• Output: PECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC12429FNTR

MC12429
PIN DESCRIPTIONS
MOTOROLA
Inputs
XTAL1, XTAL2
S_LOAD
(Int. Pulldown)
S_DATA
(Int. Pulldown)
S_CLOCK
(Int. Pulldown)
P_LOAD
(Int. Pullup)
M[8:0]
(Int. Pullup)
N[1:0]
(Int. Pullup)
OE
(Int. Pullup)
Outputs
F OUT , F OUT
TEST
Power
V CC
PLL_V CC
GND
Pin Name
S_CLOCK
PLL_V CC
S_LOAD
S_DATA
XTAL1
NC
NC
These pins form an oscillator when connected to an external series–resonant crystal.
This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this
signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this
signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition of P_LOAD for proper operation.
P_LOAD is state sensitive.
These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition of P_LOAD. M[8]
is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH transition of
P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the F OUT output.
These differential positive–referenced ECL signals (PECL) are the output of the synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or 5.0V
(V CC = PLL_V CC ). Current drain through V CC ≈ 85mA.
This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This supply is
connected to +3.3V or 5.0V (V CC = PLL_V CC ). Current drain through PLL_V CC ≈ 15mA.
These pins are the negative supply for the chip and are normally all connected to ground.
26
27
28
1
2
3
4
XTAL2
V CC
25
5
FOUT FOUT GND
OE
24
6
P_LOAD
23
7
M[0]
22
8
Figure 1. 28–Lead (Top View)
V CC
M[1]
21
9
M[2]
TEST GND
10
20
2
M[3]
11
19
18
17
16
15
14
13
12
Function
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
N[1:0]
0 0
0 1
1 0
1 1
Output Division
1
2
4
8