MPC973FA Freescale Semiconductor, MPC973FA Datasheet - Page 11

• Manufacturer Part Number: MPC973FA
• Description: IC PLL CLOCK DRIVER 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MPC973FA

• Pll: Yes with Bypass
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

exclusively to maintain the tight output–to–output skew of the
MPC973. The output waveform in Figure 15 shows a step in the
waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the 43Ω
series resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
reflection coefficient, to 2.8 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in
this case 4.0 ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 15 should be used. In this case the series terminating
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
At the load end the voltage will double, due to the near unity
Since this step is well above the threshold region it will not
MOTOROLA
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40 V
Figure 16. Optimized Dual Line Termination
Figure 15. Single versus Dual Waveforms
Ω
7 Ω + 36 Ω k 36 Ω = 50 Ω k 50 Ω
25 Ω = 25 Ω
Ω
Ω
Ω
Ω
who want to simulate their specific interconnect schemes. In
addition IV characteristics are in the process of being
generated to support the other board level simulators in general
use.
Using the Output Freeze Circuitry
computers the desire for unique power management among
system designers is keen. The individual output enable control
of the MPC973 allows designers, under software control, to
implement unique power management schemes into their
designs. Although useful, individual output control at the
expense of one pin per output is too high, therefore a simple
serial interface was derived to economize on the control pins.
which the MPC973 clock outputs may be frozen (stopped in the
logic ‘0’ state):
Serial Input Register, this register contains one program–
mable freeze enable bit for 12 of the 14 output clocks. The Qc0
and QFB outputs cannot be frozen with the serial port, this
avoids any potential lock up situation should an error occur in
the loading of the Serial Input Register. The user may program
an output clock to freeze by writing logic ‘0’ to the respective
freeze enable bit. Likewise, the user may programmably
unfreeze an output clock by writing logic ‘1’ to the respective
enable bit.
logic ‘0’ state before the time at which it would normally
transition there. The logic simply keeps the frozen clock at logic
‘0’ once it is there. Likewise, the freeze logic will never force a
newly–unfrozen clock to a logic ‘1’ state before the time at which
it would normally transition there. The logic re–enables the
unfrozen clock during the time when the respective clock would
normally be in a logic ‘0’ state, eliminating the possibility of ‘runt’
clock pulses.
Frz_Data input by supplying a logic ‘0’ start bit followed serially
by 12 NRZ freeze enable bits. The period of each Frz_Data bit
equals the period of the free–running Frz_Clk signal. The
Frz_Data serial transmission should be timed so the MPC973
can sample each Frz_Data bit with the rising edge of the
free–running Frz_Clk signal.
SPICE level output buffer models are available for engineers
With the recent advent of a “green” classification for
The freeze control logic provides a mechanism through
The freeze mechanism allows serial loading of the 12–bit
The freeze logic will never force a newly–frozen clock to a
The user may write to the Serial Input register through the
Figure 17. Freeze Data Input Protocol
MPC973
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