MPC974FA Freescale Semiconductor, MPC974FA Datasheet

MPC974FA

Manufacturer Part Number

MPC974FA

Description

IC PLL CLOCK DRIVER 52-LQFP

Manufacturer

Freescale Semiconductor

Type

Clock Driver, Fanout Distribution, Multiplexerr

Datasheet

1.MPC974FA.pdf (8 pages)

Specifications of MPC974FA

Pll

Yes with Bypass

Input

LVCMOS, LVTTL

Output

LVCMOS

Number Of Circuits

Ratio - Input:output

2:14

Differential - Input:output

No/No

Frequency - Max

125MHz

Divider/multiplier

Yes/Yes

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

52-LQFP

Frequency-max

125MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

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3.3V PLL Clock Driver

distribution chip which operates from a 3.3V supply. The MPC974 is

ideally suited for high speed, timing critical designs which need a high

level of clock fanout. The device features 15 high drive LVCMOS outputs,

each output has the capability of driving a 50

transmission line or two 50

incident edge.

of outputs. The frequency programmability offers the capability of

establishing output frequency relationships of 1:1, 2:1, 3:1, 3:2 and 3:2:1.

In addition, the device features a separate feedback output which allows

for a wide variety of input/output frequency multiplication alternatives.

The VCO_Sel pin provides an extended VCO lock range for added

flexibility and general purpose usage.

switching the PLL between two different clock sources. The PLL has been

optimized to provide small deviations in output pulse width and well

controlled, slow transition back to lock when the inputs are switched

between two references that are equal in frequency but out of phase with

each other. This feature makes the MPC974 a solution for fault tolerant

applications which require redundant clock sources.

these features please refer to the MPC993 datasheet.

various output banks and the feedback output. The MR input will reset the internal flip flops and place the outputs in high

impedance when driven LOW. The OE pin will force all of the outputs except the feedback output LOW to allow for acquiring

phase lock prior to providing clocks to the rest of the system. Note that the OE pin is not synchronized to the internal clock. As a

result, the initial pulse after de–assertion of the OE pin may be distorted. The PLL_En pin allows the PLL to be bypassed for

board level functional test. When bypassed the signal on the selected TCLK will be routed around the PLL and will drive the

internal dividers directly.

space requirements. The device is specified for 3.3V V CC .

6/00

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 2000

Fully Integrated PLL

Two Reference Clock Inputs for Redundant Clock Applications

High Impedance Output Control

Logic Enable on the Outputs

3.3V V CC Supply

Output Frequency Configurable

LQFP Packaging

The MPC974 is a fully integrated PLL based clock generator and clock

The MPC974 features 3 independent frequency programmable banks

The TCLK0 and TCLK1 inputs provide a method for dynamically

For designs in which fault tolerance is critical, other products may provide more control over the clock switch functions. For

All of the control pins are LVTTL/LVCMOS level inputs. The Fsel pins control the VCO divide ratios that are applied to the

The MPC974 is packaged in the 52–lead LQFP package to provide optimum electrical performance as well as minimize board

100ps Typical Cycle–to–Cycle Jitter

series terminated transmission lines on the

parallel terminated

REV 3

PLL CLOCK DRIVER

52–LEAD LQFP PACKAGE

LOW VOLTAGE

MPC974

CASE 848D-03

FA SUFFIX

Order this document

by MPC974/D

Related parts for MPC974FA

MPC974FA Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V PLL Clock Driver The MPC974 is a fully integrated PLL based clock generator and clock distribution chip which operates from a 3.3V supply. The MPC974 is ideally suited for high speed, timing critical designs which ...

Page 2

MPC974 39 38 Qb0 40 VCCb GNDc 43 Qc3 44 VCCc 45 Qc2 46 GNDc 47 Qc1 48 VCCc 49 Qc0 50 GNDc 51 VCO_Sel FUNCTION TABLE 1 fsela ...

Page 3

Pulldown) fsela (Int. Pulldown) TCLK_Sel (Int. Pulldown) TCLK0 0 (Int. Pullup) TCLK1 1 PLL (Int. Pullup) FB_In (Int. Pullup) PLL_EN (Int. Pulldown) VCO_Sel (Int. Pulldown) fselb (Int. Pulldown) fselc (Int. Pullup) MR (Int. Pulldown) fselFB1 (Int. Pulldown) fselFB0 (Int. ...

Page 4

MPC974 PLL INPUT REFERENCE CHARACTERISTICS ( Symbol Characteristic TCLK Input Rise/Falls f ref Reference Input Frequency f refDC Reference Input Duty Cycle 3. Input reference frequency is limited by ...

Page 5

TCLK Qa 5 FB_In QFB 33MHz fsela fselb fselc fselFB VCO_Sel 25MHz TCLK Qa 5 FB_In QFB 25MHz fsela fselb fselc fselFB VCO_Sel ...

Page 6

MPC974 Driving Transmission Lines The MPC974 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. ...

Page 7

H L– VIEW Y 3X –L– –N– –H– –T– SEATING 4X PLANE 0.05 (0.002 VIEW AA TIMING SOLUTIONS BR1333 — Rev 6 OUTLINE DIMENSIONS ...

Page 8

MPC974 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out ...

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