MC145157DW2R2 Freescale Semiconductor, MC145157DW2R2 Datasheet - Page 3

• Manufacturer Part Number: MC145157DW2R2
• Description: IC SER-IN PLL FREQ SYNTH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Type: PLL Clock/Frequency Synthesizerr

Specifications of MC145157DW2R2

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 9 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC145157DW2TR

INPUT PINS
f in
Frequency Input (Pin 1)
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
RA0 – RA2
Reference Address Inputs (Pins 5, 6, 7)
possible divide values for the total reference divider, as
defined by the table below.
logic 1 and require only a SPST switch to alter data to the
zero state.
N0 – N11
N Counter Programming Inputs (Pins 11 – 20, 22 – 25)
counter when it reaches the count of zero. N0 is the least sig-
nificant and N13 is the most significant. Pull–up resistors en-
MOTOROLA
Input to the
These three inputs establish a code defining one of eight
Pull–up resistors ensure that inputs left open remain at a
These inputs provide the data that is preset into the
OSC out
NOTE: N0 – N13 inputs and inputs RA0, RA1, and RA2 have pull–up resistors that are not shown.
OSC in
RA2
0
0
0
0
1
1
1
1
T/R
Reference Address Code
f in
N portion of the synthesizer. f in is typically
PIN DESCRIPTIONS
RA1
0
0
1
1
0
0
1
1
RA0
Freescale Semiconductor, Inc.
0
1
0
1
0
1
0
1
For More Information On This Product,
V DD
RA2
RA1
RA0
Divide
Divide
Value
Total
1024
2048
2410
8192
MC145151–2 BLOCK DIAGRAM
128
256
512
Go to: www.freescale.com
8
N13
N11
14 x 8 ROM REFERENCE DECODER
N
TRANSMIT OFFSET ADDER
14–BIT
14–BIT
N9
sure that inputs left open remain at a logic 1 and require only
an SPST switch to alter data to the zero state.
T/R
Transmit/Receive Offset Adder Input (Pin 21)
the N inputs. This is normally used for offsetting the VCO
frequency by an amount equal to the IF frequency of the
transceiver. This offset is fixed at 856 when T/R is low and
gives no offset when T/R is high. A pull–up resistor ensures
that no connection will appear as a logic 1 causing no offset
addition.
OSC in , OSC out
Reference Oscillator Input/Output (Pins 27, 26)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC in to ground and OSC out to ground.
OSC in may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSC in , but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC out .
OUTPUT PINS
PD out
Phase Detector A Output (Pin 4)
signal. Double–ended outputs are also available for this pur-
pose (see V and R ).
This input controls the offset added to the data provided at
These pins form an on–chip reference oscillator when con-
Three–state output of phase detector for use as loop–error
Frequency f V > f R or f V Leading: Negative Pulses
Frequency f V < f R or f V Lagging: Positive Pulses
Frequency f V = f R and Phase Coincidence: High–Imped-
N7 N6
ance State
R COUNTER
N COUNTER
14
14
N4
N2
MC145151–2 through MC145158–2
N0
DETECTOR
DETECTOR
DETECT
PHASE
PHASE
LOCK
B
A
LD
PD out
f V
V
R
3