MPC9772FA Freescale Semiconductor, MPC9772FA Datasheet - Page 8

• Manufacturer Part Number: MPC9772FA
• Description: IC CLOCK GEN PLL LV 1:12 52-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9772FA

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:12
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MOTOROLA
MPC9772 Configurations
the internal dividers to produce the desired output frequencies.
The output frequency can be represented by this formula:
where f
clock source (CCLKO, CCLK1 or XTAL interface), M is the PLL
feedback divider and N is a output divider. The PLL feedback
divider is configured by the FSEL_FB[2:0] and the output
dividers are individually configured for each output bank by the
FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs.
feedback-divider M is limited by the specified VCO frequency
range. f
frequency range of 200 to 480 MHz (200 to 460 MHz for ind.
temp. range) in order to achieve stable PLL operation:
a divide-by-two and can be used to situate the VCO into the
specified frequency range. This divider is controlled by the
VCO_SEL pin. VCO_SEL effectively extends the usable input
MPC9772
MPC9772 example configuration (feedback of QFB = 33.3 MHz,
f
VCO
Configuring the MPC9772 amounts to properly configuring
The reference frequency f
The PLL post-divider VCO_SEL is either a divide-by-one or
f
ref
f
Frequency Range T
REF
=400 MHz, VCO_SEL=÷1, M=12, N
= 33.3 MHz
REF
REF
QA Outputs
QA Outputs
QC Outputs
f
VCO,MIN
Input
is the reference frequency of the selected input
and M must be configured to match the VCO
Figure 3. Example Configuration
101
11
00
00
1
≤ (f
PLL
FSEL_FB[2:0]
÷M
CCLK0
CCLK1
CCLK_SEL
VCO_SEL
FB_IN
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
33.3 MHz (Feedback)
REF
A
f
OUT
MPC9772
100 – 240 MHz
16.6 – 40 MHz
16.6 – 40 MHz
50 – 120 MHz
⋅ VCO_SEL ⋅ M) ≤ f
= 0°C to +70°C T
= f
REF
÷VCO_SEL
REF
and the selection of the
QC[3:0]
QA[3:0]
QB[3:0]
⋅ M ÷ N
QFB
Freescale Semiconductor, Inc.
A
=12, N
A
For More Information On This Product,
16.6 – 38.33 MHz
16.6 – 38.33 MHz
= –40°C to +85°C
100 – 230 MHz
50 – 115 MHz
÷N
VCO,MAX
APPLICATIONS INFORMATION
B
33.3 MHz
100 MHz
200 MHz
=4, N
Go to: www.freescale.com
f
OUT
C
=2).
8
frequency range while it has no effect on the output to reference
frequency ratio.
VCO frequency and output divider:
Table 11. MPC9772 Divider
dividers and Figure 3 and Figure 4 display example
configurations for the MPC9772:
MPC9772 example configuration (feedback of QFB = 25 MHz,
f
Divider
VCO
The output frequency for each bank can be derived from the
Table 11 shows the various PLL feedback and output
N
N
N
Frequency Range T
M
f
f
f
QA[0:3]
QB[0:3]
QC[0:3]
A
B
C
f
=250 MHz, VCO_SEL=÷1, M=10, N
ref
QA Outputs
QA Outputs
QC Outputs
= 25 MHz
Input
= f
= f
= f
Figure 4. Example Configuration
Bank A Output
Bank B Output
Bank C Output
FSEL_FB[0:3]
PLL feedback
FSEL_C[0:1]
FSEL_A[0:1]
FSEL_B[0:1]
VCO
VCO
VCO
Function
Divider
Divider
Divider
011
00
00
00
1
÷ (VCO_SEL ⋅ N
÷ (VCO_SEL ⋅ N
÷ (VCO_SEL ⋅ N
FSEL_FB[2:0]
CCLK0
CCLK1
CCLK_SEL
VCO_SEL
FB_IN
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
25 MHz (Feedback)
A
100 – 240 MHz
50 – 120 MHz
50 – 120 MHz
= 0°C to +70°C T
20 – 48 MHz
MPC9772
VCO_SEL
QA[3:0]
QB[3:0]
QC[3:0]
÷1
÷2
÷1
÷2
÷1
÷2
÷1
÷2
A
B
C
QFB
)
)
)
A
A
TIMING SOLUTIONS
=4, N
8, 12, 16, 20, 24, 32,
= –40°C to +85°C
100 – 230 MHz
50 – 115 MHz
50 – 115 MHz
4, 6, 8, 10, 12, 16
20 – 46 MHz
8, 12, 16, 24
8, 12, 16, 20
4, 8, 12, 16
4, 6, 8, 12
4, 6, 8, 10
B
2, 4, 6, 8
Values
=4, N
62.5 MHz
62.5 MHz
125 MHz
40
C
=2).