MPC9229AC Freescale Semiconductor, MPC9229AC Datasheet - Page 3

• Manufacturer Part Number: MPC9229AC
• Description: IC PECL CLOCK SYNTHESIZER 32LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock/Frequency Synthesizer, Clock Generatorr

Specifications of MPC9229AC

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SOLUTIONS
Table 1. Pin Configuration
XTAL_IN, XTAL_OUT
FOUT, FOUT
TEST
S_LOAD
P_LOAD
S_DATA
S_CLOCK
M[0:8]
N[1:0]
OE
GND
V
VCC_PLL
CC
Pin
Output
Output
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
I/O
Default
Supply
Supply
Supply
Table 2. Output frequency range and PLL Post-divider N
0
1
0
0
1
1
1
Freescale Semiconductor, Inc.
1
0
0
1
1
For More Information On This Product,
N
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVPECL
Ground
Analog
Type
V
V
CC
CC
0
0
1
0
1
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Crystal oscillator interface
Differential clock output
Test and device diagnosis output
Serial configuration control input.
This inputs controls the loading of the configuration latches with the contents of
the shift register. The latches will be transparent when this signal is high, thus the
data must be stable on the high-to-low transition.
Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive
Serial configuration data input.
Serial configuration clock input.
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of
runt pulses on the F
(F
Negative power supply (GND)
Positive power supply for I/O and core. All V
positive power supply for correct operation
PLL positive power supply (analog power supply)
O
Output division
OUT
= L, FOUT = H)
1
2
4
8
di i i
3
OUT
output. OE = L low stops F
O
Output frequency range
200 - 400 MHz
100 - 200 MHz
50 - 100 MHz
25 - 50 MHz
f
Function
CC
pins must be connected to the
OUT
in the logic low state
MPC9229
MOTOROLA