MPC9658AC Freescale Semiconductor, MPC9658AC Datasheet - Page 3

• Manufacturer Part Number: MPC9658AC
• Description: IC PLL CLK GENERATOR 1:10 32LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9658AC

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced Clock Drivers Device Data
Freescale Semiconductor
Table 1. Pin Configurations
Table 2. Function Table
Table 3. Absolute Maximum Ratings
PCLK, PCLK
FB_IN
VCO_SEL
BYPASS
PLL_EN
MR/OE
Q0–9
QFB
GND
V
V
PLL_EN
BYPASS
VCO_SEL
MR/OE
1. PLL operation requires BYPASS = 1 and PLL_EN = 1.
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
Symbol
CC_PLL
CC
Control
V
I
V
V
OUT
I
T
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
OUT
CC
IN
Number
IN
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
1
1
1
0
Default
Input
Input
Input
Input
Input
Input
Output
Output
Supply
Supply
Supply
Name
Test mode with PLL bypassed. The reference clock
(PCLK) is substituted for the internal VCO output.
MPC9658 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9658 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
VCO ÷ 1 (High frequency range). f
Outputs enabled (active)
Characteristics
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
V
CC
CC
Type
(1)
0
PECL reference clock signal
PLL feedback signal input, connect to QFB
Operating frequency range select
PLL and output divider bypass select
PLL enable/disable
Output enable/disable (high-impedance tristate) and device reset
Clock outputs
Clock output for PLL feedback, connect to FB_IN
Negative power supply (GND)
PLL positive power supply (analog power supply). It is recommended to use an external
RC filter for the analog power supply pin V
INFORMATION
Positive power supply for I/O and core. All V
power supply for correct operation.
REF
= f
Q0–9
= 2 ⋅ f
for details.
–0.3
–0.3
–0.3
VCO
Min
–65
Selects the VCO output.
Selects the output dividers.
VCO ÷ 2 (Low output range). f
Outputs disabled (high-impedance state) and reset of the
device. During reset the PLL feedback loop is open. The
VCO is tied to its lowest frequency. The length of the reset
pulse should be greater than one reference clock cycle
(PCLK).
Description
CC_PLL
V
V
CC
CC
CC
Max
±20
±50
125
3.9
pins must be connected to the positive
+0.3
+0.3
. Refer to
(1)
1
APPLICATIONS
REF
Unit
= f
mA
mA
°C
V
V
V
Q0–9
= 4 ⋅ f
Condition
MPC9658
VCO
3