CS82C54-10Z96 Intersil, CS82C54-10Z96 Datasheet - Page 5
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CS82C54-10Z96
Manufacturer Part Number
CS82C54-10Z96
Description
IC TIMER INTERVAL 10MHZ 28-PLCC
Manufacturer
Intersil
Type
Programmable Timerr
Datasheet
1.CS82C54Z96.pdf
(22 pages)
Specifications of CS82C54-10Z96
Frequency
10MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
10mA
Operating Temperature
0°C ~ 70°C
Package / Case
28-PLCC
Rohs Compliant
YES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Other names
CS82C54-10Z96TR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS82C54-10Z96
Manufacturer:
Intersil
Quantity:
2 250
Company:
Part Number:
CS82C54-10Z96
Manufacturer:
Intersil
Quantity:
2 150
Part Number:
CS82C54-10Z96
Manufacturer:
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Quantity:
20 000
Functional Diagram
Pin Description
SYMBOL
GATE 0
GATE 1
GATE 2
D7 - D0
OUT 0
OUT 1
OUT 2
A0, A1
D
CLK 0
CLK 1
CLK 2
GND
V
WR
7
RD
CS
CC
- D
WR
RD
CS
A
A
0
0
1
8
NUMBER
DIP PIN
REGISTER
CONTROL
19 - 20
1 - 8
BUFFER
WORD
WRITE
LOGIC
10
11
12
13
14
15
16
17
18
21
22
23
24
DATA/
READ/
9
BUS
TYPE
5
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
-
DATA: Bi-directional three-state data bus lines, connected to system data bus.
CLOCK 0: Clock input of Counter 0.
OUT 0: Output of Counter 0.
GATE 0: Gate input of Counter 0.
GROUND: Power supply connection.
OUT 1: Output of Counter 1.
GATE 1: Gate input of Counter 1.
CLOCK 1: Clock input of Counter 1.
GATE 2: Gate input of Counter 2.
OUT 2: Output of Counter 2.
CLOCK 2: Clock input of Counter 2.
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and WR
are ignored otherwise.
READ: This input is low during CPU read operations.
WRITE: This input is low during CPU write operations.
V
decoupling.
CC
: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended for
COUNTER
COUNTER
COUNTER
0
1
2
CLK 0
GATE 0
OUT 0
CLK 1
GATE 1
OUT 1
CLK 2
GATE 2
OUT 2
82C54
CLK n
A1
0
0
1
1
REGISTER
CONTROL
CONTROL
GATE n
WORD
LOGIC
OUT n
A0
0
1
0
1
REGISTER
DEFINITION
STATUS
STATUS
LATCH
COUNTER INTERNAL BLOCK DIAGRAM
Counter 0
Counter 1
Counter 2
Control Word Register
INTERNAL BUS
SELECTS
CR
OL
M
M
CE
CR
OL
L
L