ISL12022IBZ Intersil, ISL12022IBZ Datasheet - Page 20

• Manufacturer Part Number: ISL12022IBZ
• Description: IC RTC/CALENDAR TEMP SNSR 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022IBZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Once the registers are set, the following waveform will be
seen at IRQ/F
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
Time Stamp V
The TSV2B Register bytes are identical to the RTC register
bytes, except they do not extend beyond the Month. The Time
Stamp captures the FIRST V
time, and will not update upon subsequent events, until cleared
(only the first event is captured before clearing). Set CLRTS = 1
to clear this register (Add 09h, PWR_V
Note that the time stamp registers are cleared to all “0”,
including the month and day, which is different from the RTC
and alarm registers (those registers default to 01h). This is
the indicator that no time stamping has occurred since the
last clear or initial power-up. Once a time stamp occurs,
there will be a non-zero time stamp.
Time Stamp Battery to V
The Time Stamp Battery to V
to the RTC register bytes, except they do not extend beyond
Month. The Time Stamp captures the LAST transition of
V
events is retained). Set CLRTS = 1 to clear this register (Add
09h, PWR_V
ADDRESS
BAT
ADDRESS
24h
25h
26h
27h
20h
21h
22h
23h
to V
D
RTC AND ALARM REGISTERS ARE BOTH “30s”
(only the last event of a series of power-up/down
DD
FIGURE 13. IRQ/F
Month Reverse
OUT
Month Forward
Hour Reverse
Date Reverse
Day Reverse
Hour Forward
Date Forward
Day Forward
FUNCTION
DD
register).
NAME
:
to Battery Registers (TSV2B)
DD
60s
20
DD
DD
OUT
to Battery Voltage transition
Register bytes are identical
Registers (TSB2V)
DSTE
WAVEFORM
7
0
0
0
0
7
0
0
0
DD
register).
DwFdE
DwRvE
TABLE 20. DST FORWARD REGISTERS
TABLE 21. DST REVERSE REGISTERS
6
0
0
0
6
0
0
0
WkFd12
HrFd21
DtFd21
WkRv12
DtRv21
HrRv21
ISL12022
5
0
5
0
DST Control Registers (DSTCR)
8 bytes of control registers have been assigned for the
Daylight Savings Time (DST) functions. DST beginning (set
Forward) time is controlled by the registers DstMoFd,
DstDwFd, DstDtFd, and DstHrFd. DST ending time (set
Backward or Reverse) is controlled by DstMoRv, DstDwRv,
DstDtRv and DstHrRv.
Tables 20 and 21 describe the structure and functions of the
DSTCR.
DST FORWARD REGISTERS (20H TO 23H)
DST forward is controlled by the following DST Registers:
DST Enable
DSTE is the DST Enabling Bit located in Bit 7 of register 20h
(DstMoFdxx). Set DSTE = 1 will enable the DSTE function.
Upon powering up for the first time (including battery), the
DSTE bit defaults to “0”. When DSTE is set to “1” the RTC
time must be at least one hour before the scheduled DST
time change for the correction to take place. When DSTE is
set to “0”, the DSTADJ bit in the Status Register
automatically resets to “0”.
DST Month Forward
DstMoFd sets the Month that DST starts. The format is the
same as for the RTC register month, from 1 to 12. The
default value for the DST begin month is 00h.
MoFd20
WkFd11
MoRv20
DtFd20
HrFd20
WkRv11
DtRv20
HrRv20
4
4
MoFd13
WkFd10
WkRv10
MoRv13
DtFd13
HrFd13
DtRv13
HrRv13
3
3
DwRv12
MoRv12
MoFd12
DwFd12
DtRv12
HrRv12
HrFd12
DtFd12
2
2
MoRv11
DwRv11
HrRv11
MoFd11
DwFd11
DtRv11
HrFd11
DtFd11
1
1
DwRv10
June 23, 2009
MoFd10
DwFd10
MoRv10
DtRv10
HrRv10
DtFd10
HrFd10
FN6659.2
0
0