DS1374U-3+ Maxim Integrated Products, DS1374U-3+ Datasheet - Page 12

• Manufacturer Part Number: DS1374U-3+
• Description: IC RTC I2C W/CHARGER 10-USOP
• Manufacturer: Maxim Integrated Products
• Type: Watchdog Timer/Trickle Chargerr

Specifications of DS1374U-3+

• Time Format: Binary
• Date Format: Binary
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

The DS1374 has two additional registers (07h–08h) that
control the WD/ALM counter and the square-wave, inter-
rupt, and reset outputs.
Bit 7/Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped. When this bit is set to logic 1, the oscilla-
tor is stopped and the DS1374 is placed into a
low-power standby mode (I
0) when power is first applied. When the DS1374 is
powered by V
of the state of the EOSC bit.
Bit 6/WD/A A L L M M Counter Enable (WACE). When set to
logic 1, the WD/ALM counter is enabled. When set to
logic 0, the WD/ALM counter is disabled, and the 24
bits can be used as NV RAM. This bit is clear (logic 0)
when power is first applied.
Bit 5/WD/A A L L M M Counter Select (WD/ALM). When set to
logic 0, the counter decrements every second until it
reaches zero and is then reloaded and restarted. When
set to logic 1, the WD/ALM counter decrements every
1/4096 of a second (approximately every 244µs) until it
reaches zero, sets the AF bit in the status register, and
stops. If any of the WD/ALM counter registers are
accessed before the counter reaches zero, the counter
is reloaded and restarted. This bit is clear (logic 0)
when power is first applied.
Bit 4/Battery-Backed Square-Wave Enable (BBSQW).
This bit, when set to logic 1, enables the square-wave
output when V
being powered by the V
I
Trickle Charger and Reset Input/Output
12
2
C, 32-Bit Binary Counter Watchdog RTC with
EOSC
Bit 7
____________________________________________________________________
Special Purpose Registers
CC
CC
, the oscillator is always on regardless
WACE
is absent and when the DS1374 is
Bit 6
BACKUP
Control Register (07h)
DDR
). This bit is clear (logic
WD/ALM
pin. When BBSQW is
Bit 5
BBSQW
Bit 4
logic 0, the SQW pin goes high impedance when V
falls below the power-fail trip point. This bit is disabled
(logic 0) when power is first applied.
Bit 3/Watchdog Reset Steering Bit (WDSTR). This bit
selects which output pin the watchdog-reset signal
occurs on. When the WDSTR bit is set to logic 0, a
250ms pulse occurs on the RST pin if WD/ALM = 1 and
the WD/ALM counter reaches zero. The 250ms reset
pulse occurs on the INT pin when the WDSTR bit is set
to logic 1. This bit is logic 0 when power is first applied.
Bits 2, 1/Rate Select (RS2 and RS1). These bits con-
trol the frequency of the square-wave output when the
square wave has been enabled. Table 4 shows the
square-wave frequencies that can be selected with the
RS bits. These bits are both set (logic 1) when power is
first applied.
Bit 0/Alarm Interrupt Enable (AIE). When set to logic
1, this bit permits the alarm flag (AF) bit in the status
register to assert INT (when WDSTR = 1). When set to
logic 0 or WDSTR is set to logic 0, the AF bit does not
initiate the INT signal. If the WD/ALM bit is set to logic 1
and the AF flag is set, writing AIE to zero does not trun-
cate the 250ms pulse on the INT pin. The AIE bit is at
logic 0 when power is first applied. The INT output is
available while the device is powered by either supply.
Table 4. Square-Wave Output Frequency
RS2
WDSTR
0
0
1
1
Bit 3
RS1
0
1
0
1
SQUARE-WAVE OUTPUT FREQUENCY
Bit 2
RS2
32.768kHz
4.096kHz
8.192kHz
Bit 1
RS1
1Hz
Bit 0
AIE
CC