DS1302ZN+ Maxim Integrated Products, DS1302ZN+ Datasheet - Page 11

• Manufacturer Part Number: DS1302ZN+
• Description: IC TIMEKEEPER T-CHARGE IND 8SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Trickle-Chargerr

Specifications of DS1302ZN+

• Memory Size: 31B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: 3-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Function: Clock/Calendar/Trickle Charger/NV Timekeeping RAM
• Rtc Memory Size: 31 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (3-Wire)
• Supply Current: 1.2 mA
• Clock Format: HH
• Clock Ic Type: RTC
• Ic Interface Type: 3 Wire
• Memory Configuration: 31 X 8
• Supply Voltage Range: 2V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3. Data Transfer on I
Depending upon the state of the R/W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the
2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received
byte. Data is transferred with the most significant bit (MSB) first.
by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number
of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the
end of the last received byte, a “not acknowledge” is returned.
The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also
the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most
significant bit (MSB) first.
SDA
SCL
CONDITION
START
MSB
1
2
2
C Serial Bus
6
7
DIRECTION
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
R/ W
BIT
8
ACK
9
11 of 14
1
REPEATED IF MORE BYTES
2
ARE TRANSFERED
DS1307 64 x 8, Serial, I
SIGNAL FROM RECEIVER
3-7
ACKNOWLEDGEMENT
8
ACK
9
2
C Real-Time Clock
CONDITION
CONDITION
REPEATED
START
STOP
OR