M41T00SM6F STMicroelectronics, M41T00SM6F Datasheet - Page 7

• Manufacturer Part Number: M41T00SM6F
• Description: IC RTC SERIAL ACCESS 8-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/NVSRAMr

Specifications of M41T00SM6F

• Memory Size: 8B
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6458-2; M41T00SM6F

2
2.1
2.1.1
2.1.2
Operation
The M41T00S clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1.
2.
3.
4.
5.
6.
7.
8.
The M41T00S clock continually monitors V
fall below V
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. Once V
switchover voltage (V
down into an ultra-low current mode of operation to preserve battery life. If V
V
greater than V
V
above V
For more information on battery storage life refer to Application Note AN1012.
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
●
●
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
PFD
PFD
Seconds register
Minutes register
Century/hours register
Day register
Date register
Month register
Year register
Calibration register
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
, the device power is switched from V
. Upon power-up, the device switches from battery to V
PFD
PFD
, it will recognize the inputs.
PFD
, the device terminates an access in progress and resets the device address
, the device power is switched from V
SO
), the device automatically switches over to the battery and powers
CC
CC
to V
for an out-of-tolerance condition. Should V
BAT
when V
CC
to V
CC
CC
BAT
at V
drops below V
when V
SO
. When V
CC
CC
BAT
falls below the
drops below
BAT
CC
is less than
. If V
rises
BAT
7/26
CC
is