M48T35AV-10MH1F STMicroelectronics, M48T35AV-10MH1F Datasheet - Page 10

• Manufacturer Part Number: M48T35AV-10MH1F
• Description: IC TIMEKPR NVRAM 256KB 3V 28SOIC
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T35AV-10MH1F

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4714-2

Operation modes
2.2
10/29
WRITE mode
The M48T35AV is in the WRITE mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t
cycles to avoid bus contention; however, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
Figure 6.
Figure 7.
A0-A14
E
W
DQ0-DQ7
A0-A14
E
W
DQ0-DQ7
WRITE enable controlled, WRITE mode AC waveform
Chip enable controlled, WRITE mode AC waveforms
tAVEL
tAVEL
tAVWL
tAVWL
Doc ID 6845 Rev 8
tWLQZ
EHAX
WHDX
tAVWH
from chip enable or t
tAVEH
afterward. G should be kept high during WRITE
tWLWH
VALID
tAVAV
WLQZ
tAVAV
VALID
tELEH
after W falls.
tDVEH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
WHAX
from WRITE enable prior
tEHDX
tWHQX
DVWH
tEHAX
tWHAX
prior to the
M48T35AV
AI00926
AI00927