DS1388Z-3+T&R Maxim Integrated Products, DS1388Z-3+T&R Datasheet - Page 6

• Manufacturer Part Number: DS1388Z-3+T&R
• Description: IC RTC I2C W/CHARGER 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of DS1388Z-3+T&R

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
and 512 Bytes EEPROM
WARNING: Under no circumstances are negative undershoots, of any
amplitude, allowed when device is in write protection.
6
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: Specified with I
Note 11: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 12: After this period, the first clock pulse is generated.
Note 13: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
Note 14: The maximum t
Note 15: A fast-mode device can be used in a standard-mode system, but the requirement t
Note 16: C
Note 17: The parameter t
Note 18: If the oscillator is disabled or stopped, RST goes inactive after t
2
C RTC/Supervisor with Trickle Charger
_____________________________________________________________________
Limits at -40°C are guaranteed by design and are not production tested.
All voltages are referenced to ground.
Measured at V
The use of the 250Ω trickle-charge resistor is not allowed at V
Measured at V
Measured at V
The RST pin has an internal 50kΩ pullup resistor to V
I
to bridge the undefined region of the falling edge of SCL.
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
before the SCL line is released.
range of 0V ≤ V
CCA
B
—total capacitance of one bus line in pF.
—SCL clocking at max frequency = 400kHz.
CC
CC
CC
2
HD:DAT
CC
OSF
C bus inactive.
= typ, V
= typ, V
= typ, V
≤ V
is the period of time that the oscillator must be stopped for the OSF flag to be set over the voltage
CC(MAX)
need only be met if the device does not stretch the LOW period (t
BACKUP
BACKUP
BACKUP
and 1.3V ≤ V
= 0V, register 0Ah, block 0h = A5h.
= 0V, register 0Ah, block 0h = A6h.
= 0V, register 0Ah, block 0h = A7h.
BACKUP
≤ 3.7V.
CC
.
CC
RST
> 3.63V and should not be enabled.
plus the startup time of the oscillator.
R(MAX)
SU:DAT
+ t
SU:DAT
LOW
≥ 250ns must then be met. This
) of the SCL signal.
= 1000 + 250 = 1250ns
IHMIN
of the SCL signal)